Signal calibration method, device, chip and storage medium
A calibration method and signal technology, applied in the field of radio frequency, can solve the problems of waste of human and material resources, time-consuming and laborious, etc.
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Embodiment 1
[0040] figure 2 A flow chart of a signal correction method provided in Embodiment 1 of the present invention, the method can be executed by a signal correction device, the device can be implemented by software and / or hardware, and the device can be integrated in an ISM frequency band In the transceiver, the transceiver consists of a direct conversion transmitter and a low-IF receiver. The transceiver module is utilized to the greatest extent, and the I / Q mismatch can be corrected through a one-time correction when the chip is factory-initialized. like figure 2 As shown, the method includes:
[0041] S110. Construct a mismatch model based on a preset offset matrix, an adjustment matrix, and a standard quadrature test signal.
[0042] Among them, the standard quadrature test signal The frequency can be 1.536MHz, and the digital-to-analog converter (DAC) operates at 122.88MHz, so the test signal has 80 sampling points per cycle. The test signal is a continuous sine wave f...
Embodiment 2
[0075] Figure 4 A structural block diagram of a signal correction device provided in Embodiment 2 of the present invention, such as Figure 4 As shown, the device includes: a mismatch model construction module 210 , a parameter adjustment module 220 and a target parameter determination module 230 . in,
[0076] A mismatch model building module 210, configured to build a mismatch model based on a preset offset matrix, an adjustment matrix, and a standard quadrature test signal;
[0077] The parameter adjustment module 220 is used to adjust the parameters of the target circuit by taking the direction in which the signal strength of the image signal decreases as the adjustment direction after the preset orthogonal test signal is modulated;
[0078] The target parameter determination module 230 is configured to determine an optimal adjustment matrix based on the successive approximation method and the inverse matrix of the preset offset matrix, and use the current parameters of...
Embodiment 3
[0107] Figure 5 It is a schematic structural diagram of a chip provided by Embodiment 3 of the present invention. Figure 5 A block diagram of an exemplary chip 12 suitable for use in implementing embodiments of the invention is shown. Figure 5 The chip 12 shown is only an example, and should not limit the functions and scope of use of the embodiments of the present invention.
[0108] like Figure 5 As shown, chip 12 takes the form of a general-purpose computing chip. Components of chip 12 may include, but are not limited to: one or more processors or processing units 16 , system memory 28 , bus 18 connecting various system components including system memory 28 and processing unit 16 .
[0109] Bus 18 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processor, or a local bus using any of a variety of bus structures. These architectures include, by way of example, but...
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