A cmos inverter and electronic device

Abstract

The invention provides a CMOS inverter and an electronic device, the CMOS inverter comprising: a semiconductor substrate; a first MOS transistor includes a first source electrode and a first drain electrode, wherein the first source electrode and the first drain electrode are respectively arranged in semiconductor substrates on both sides of the control gate electrode and have a first conductivitytype; A control gate disposed on a surface of the semiconductor substrate; A semiconductor material layer suspended above the semiconductor substrate with at least a portion of the control gate as asupport and extending outwardly of the control gate side walls; A second MOS transistor including a second source and a second drain, the second source and the second drain being disposed in the semiconductor material layers on both sides of the control gate, respectively, and having a second conductivity type, wherein the first MOS transistor and the second MOS transistor share the control gate.The CMOS inverter of the invention has higher performance, smaller area and higher reliability.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a CMOS inverter and an electronic device. Background technique [0002] The CMOS inverter is another semiconductor basic component composed of two complementary PMOS and NMOS. The inverter can reverse the phase of the input signal by 180 degrees and is widely used in analog circuits. [0003] Such as figure 1 Shown is a schematic cross-sectional view of a traditional CMOS inverter, wherein the CMOS inverter is composed of two special-shaped MOS transistors in parallel, an NMOS transistor 10 and a PMOS transistor 11, and the NMOS transistor 10 is connected to the gate of the PMOS transistor 11 as The input of the inverter V IN ; The drain of the NMOS transistor 10 is connected to the drain of the PMOS transistor 11 as the output terminal V of the inverter OUT ; The source of the NMOS tube is connected to the low potential end or grounded V SS ; The source of the PMOS tu...

AI Technical Summary

Problems solved by technology

[0004] The two CMOS transistors and the p-type substrate form a parasitic circuit, which is very easy to form a latch-up effect, causing the circuit to fail or even burn out

Although the two MOS tubes will be separated by the isolation layer, there are still many parasitic capacitances; if the isolation layer is not done well, the parasitic circuit will easily produce a latch-up effect, causing the circuit to fail or even burn out

Images