Layout parameter extraction method of polygonal spiral inductor

Abstract

The invention relates to a layout parameter extraction method of a polygonal spiral inductor device, A technology for manufacture semiconductor integrated circuit, The polygonal spiral inductor devicecomprises a first lead wire, a second lead wire and an outer coil protection ring. The method comprises the following steps: an auxiliary layer is drawn, the auxiliary layer is rectangular, two opposite sides of the auxiliary layer are respectively coincident with the inner walls of the first lead wire and the second lead wire, and the other two opposite sides of the auxiliary layer are respectively coincident with the inner walls of the outer coil protection ring; Using the position relationship of the auxiliary layer with the first lead wire, the second lead wire and the inner wall of the outer coil protection ring, the derivative inner diameter rectangle of the spiral inductance coil of the inductor device is generated by the electronic design automation tool EDA. The derivative innerdiameter rectangle of the spiral inductance coil of the inductor device is generated by the position relationship of the auxiliary layer with the first lead wire, the second lead wire and the inner wall of the outer coil protection ring. Generate the technical document of calculating the inner diameter R and the number of turns N of the inductance coil by the EDA tool. As well as the operation technical document, extracts the inductor device parameter, in order to accurately extracts the inductor device parameter, enhances the inductor device layout drawing efficiency, reduces the error risk.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit manufacturing technology, in particular to a layout parameter extraction method of a polygonal spiral inductance device. Background technique [0002] In semiconductor integrated circuit technology, with the development of integration technology, the process nodes of integrated circuit manufacturing continue to decrease, and system-on-chip (SOC) has become a design hotspot. In the field of radio frequency integrated circuit (RFIC) design, designers use radio frequency system-on-chip (RF SOC) design. In RF system-on-chip (RF SOC) design, designers will choose a chip-level planar inductor structure instead of the traditional spiral tube structure to achieve the design requirements of small area, high inductor quality factor (Q), and low power consumption. [0003] The planar inductance structure that is widely used at present is to use the subsequent metal interconnection process to make the to...

AI Technical Summary

Problems solved by technology

The current layout parameter extraction method of inductance devices is to draw various special auxiliary layers, and then extract each parameter according to various special auxiliary layers, so it is not compatible with various customers, increases the difficulty of design, and increases the complexity of the corresponding design rule check (DRC) , reducing layout drawing efficiency

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