A semiconductor memory aging test core board

Abstract

The invention belongs to the technical field of semiconductor memory aging test, A semiconductor memory aging test core board is disclosed, According to the parameter configuration of the host computer, the test vectors are generated in real time, various types of test signals and test patterns are output, and the test signals are delayed and adjusted, the driving is strengthened, the waveform control is processed, and the power signals are compensated to generate more accurate power signals of the test signals. Users' customization ability and flexibility to test waveforms are improved. The test core board has a partitioned memory, which stores the real-time comparison test data in the test process, and controls and analyzes the failure DUT test process through the partitioned stored data, thus realizing the control and failure analysis of a single DUT test process in the aging test. The storage space provided by the memory such as DRAM stores each IO of each DUT long enough to enablethe DUT manufacturer to perform statistical analysis on each batch of failed DUT, thereby improving yield and improving product reliability.

Description

technical field [0001] The invention belongs to the technical field of semiconductor memory burn-in test, and more specifically relates to a semiconductor memory burn-in test core board. Background technique [0002] Semiconductor memory has a certain failure probability, and the relationship between the failure probability and the number of times of use conforms to the characteristics of the bathtub curve. The failure probability of the memory is high at the beginning of use, and the failure probability is greatly reduced after a certain number of times of use, until it is close to or reaches its use. After the lifetime, the failure probability of the memory will increase again. So far, no memory manufacturer has dared to ignore the failure problem of semiconductor memory. Generally, the aging test (Test During burn-in, TDBI) is used to accelerate the occurrence of memory failure probability, and directly let it enter the product stable period to solve this problem. [000...

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Problems solved by technology

[0010] The Chinese patent with the publication number CN102467973A discloses a memory testing method and device, which mentions that when the memory is aging, the heat generated by its own power consumption is used to control the aging temperature, so as to solve the problem of uneven temperature distribution and temperature error caused by external heating. It is mentioned that the controller and signal generator are used to test the memory, and the row-column matrix control method is mainly used; however, it does not involve the recording and management analysis of the test process, and this method is not suitable for low-temperature aging test

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