Manufacturing method of 3D memory device and 3D memory device

Abstract

The present application discloses a manufacturing method of a 3D storage device and the 3D storage device. The manufacturing method of a 3D memory device includes: forming a gate stack structure above a substrate; forming a plurality of channel pillars penetrating through the gate stack structure, including an epitaxial layer at the bottom of the plurality of channel pillars, extending to the substrate; forming an ONOPO structure on the sidewalls of the plurality of channel columns; and removing the ONOPO structure located above the epitaxial layer to expose at least part of the upper surface of the epitaxial layer, wherein the removal is located on the epitaxial layer The steps of the ONOPO structure above the layers are performed step by step. The manufacturing method of the 3D memory device adopts the method of etching the ONOPO structure step by step, which can conveniently control the etching depth of the recessed area on the epitaxial layer surface at the bottom of the channel column, reduces the process difficulty of controlling the etching depth, and avoids the problem of underetching or over-etching. The problem of circuit breakage occurs due to etching, thereby improving the yield and reliability of 3D memory devices.

Description

technical field [0001] The present invention relates to memory technology, and more specifically, to a manufacturing method of a 3D memory device and a 3D memory device. Background technique [0002] The improvement of the storage density of the memory device is closely related to the progress of the semiconductor manufacturing process. As the feature size of the semiconductor manufacturing process becomes smaller and smaller, the storage density of the memory device becomes higher and higher. In order to further increase storage density, memory devices with a three-dimensional structure (ie, 3D memory devices) have been developed. A 3D memory device includes a plurality of memory cells stacked in a vertical direction, which can double the integration level on a wafer per unit area and reduce the cost. [0003] Existing 3D memory devices are mainly used as non-volatile flash memory. The two main non-volatile flash memory technologies use NAND and NOR structures, respectiv...

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Problems solved by technology

[0004] In the prior art, when manufacturing 3D memory devices, when etching the ONOPO (Oxide-Nitride-Oxide-Polysilicon-Oxide) structure at the bottom of the channel pillar, a single-step method is often used to directly remove the The ONOPO structure on the surface of the layer, due to the deformation or warping of the channel column, will lead to the problem of uneven etching depth of the epitaxial layer at the bottom of the channel column

Moreover, due to the under etch effect (under etch defect) and over etch (over etch) effect, the epitaxial layer at the bottom of some channel pillars will be under-etched or over-etched, resulting in a gap between the select gate transistor and the storage transistor or the substrate. There is an open circuit between the CMOS circuit and the gate conductor, which affects the yield and reliability of the 3D memory device

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