Semiconductor device structure and manufacturing method

Abstract

The invention discloses a semiconductor device structure. The semiconductor device is manufactured by using a conventional semiconductor substrate. Complete dielectric isolation between devices is realized through back trench isolation and isolation and connection of shallow trenches. Back trenches isolate the bottom from contacting N+ source-drain and P+ source-drain, eliminate parasitic capacitance among N+ source-drain, the P+ source-drain and an N-well, and improve switching speed of a MOS device. Through processes of back surface N+ injection and P+ injection, back contact holes and a back surface metal layer, a P-well of a NMOS is connected with ground and an N-well of the PMOS is connected with a power supply are realized, series resistance of body-contact is reduced, thereby preventing a floating body effect of a SOI device. The back contact hole is connected with the N+ injection and the P+ injection on the silicon substrate, and heat generated in the device can be quickly guided out through the contact hole and the metal layer, thereby preventing a self-heating effect and preventing deterioration of device performance. The invention also discloses a manufacturing method for the semiconductor device structure.

Description

technical field [0001] The present invention relates to the technical field of semiconductor processing, and more specifically, to a semiconductor device structure and manufacturing method. Background technique [0002] For half a century, the semiconductor industry has followed Moore's Law to shrink transistor size, increase transistor density, and improve performance step by step. However, as the size of bulk silicon transistor devices with planar structure is getting closer to the physical limit, Moore's law is getting closer to its end; therefore, some new structures of semiconductor devices called "non-classical CMOS" have been proposed. These technologies include FinFET, carbon nanotubes and silicon on insulator (silicon on insulator, SOI), silicon germanium on insulator (SiGe on insulator: SiGeOI) and germanium on insulator (Ge on insulator: GeOI), etc. Through these new structures, the performance of semiconductor devices can be further improved. [0003] Among the...

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Problems solved by technology

But because the device is fully isolated, the NMOS in Figure 1 And the body region 14 of the PMOS cannot be effectively connected to the power supply or the ground, forming the so-called floating body effect

Although the floating body effect can be improved through the device layout, due to the large resistance of the body region 14, when the body contact region is far away from the channel region, the floating body effect will still appear, resulting in an abnormal output curve of the MOS transistor

At the same time, the thermal conductivity of the silicon dioxide 12 below the body region 14 is poor, which causes the self-heating effect of the device, reduces the carrier mobility of the device, and degrades the performance of the device.

In addition, the preparation process of SOI silicon wafer is complicated and the manufacturing cost is high

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