Chip package structure and method for forming same

A chip packaging structure and wafer technology, applied in electrical components, electrical solid devices, circuits, etc., can solve the problems affecting the performance of the packaging structure, reducing the size of semiconductor packaging, wafer peeling, etc., to improve packaging performance, improve warpage and Delamination phenomenon, the effect of reducing the thermal expansion coefficient
CN109712966AInactive Publication Date: 2019-05-03SEMICON MFG INT (SHANGHAI) CORP +1
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Patent Information

Authority / Receiving Office
CN Β· China
Patent Type
Applications(China)
Current Assignee / Owner
SEMICON MFG INT (SHANGHAI) CORP
Publication Date
2019-05-03
Estimated Expiration
Not applicable Β· inactive patent

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Abstract

The invention provides a chip package structure and a method for forming the same. By replacing all or a part of primer in a gap between two adjacent wafer stacks with a molding layer having a low thermal expansion coefficient, the amount of the primer is reduced and the thermal expansion coefficient of a packaging colloid composed of the molding layer and the primer is reduced, thereby reducing the CTE mismatch difference between the packaging colloid and the wafer stack and between the packaging colloid and a substrate, improving the warpage and the stratification of the substrate and the wafer stack, and improving packaging performance.
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Description

technical field

[0001] The invention relates to the technical field of integrated circuit manufacturing, in particular to a chip packaging structure and a forming method thereof. Background technique

[0002] Chip on wafer (CoW) packaging technology, as one of the advanced packaging (Package) technologies, can stack multiple chips separately on the positions of good chips that are pre-identified on a device wafer (Device Wafer) (Die, that is, a block with complete functions cut out from the wafer) to meet different functions, and then realize the manufacture of three-dimensional semiconductor integrated circuit (IC) products. CoW packaging technology has many advantages, such as the ability to achieve high integration of semiconductor devices, reduce the size of semiconductor packages, reduce the cost of final products, simplify assembly processes, and improve yields. After the wafer level molding (wafer level molding) step is completed, the problem of wafer warpage (wafer ...

Claims

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