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A kind of fce diode and its manufacturing method

A manufacturing method and trench technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problem of reducing the contact effect between the P++ doped region 201 and the second metal layer 106, weakening the soft recovery characteristics of FCE diodes, etc. problems, to achieve the effect of reducing contact resistance

Active Publication Date: 2021-10-01
ZHUZHOU CRRC TIMES SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] because figure 2 The N-type ions of the N++ doped layer 104 and the P-type ion concentrations of the P++ doped region 201 in the N++ doped layer 104 are all very high, so that the N-type ions of the N++ doped layer 104 and the P-type ions of the P++ doped region 201 are easily mixed in the P++ The impurity regions compensate each other, reducing the contact effect between the P++ doped region 201 and the second metal layer 106
If the concentration of N-type ions in the N++ doped layer 104 is reduced, the soft recovery characteristics of the FCE diode will be weakened

Method used

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  • A kind of fce diode and its manufacturing method
  • A kind of fce diode and its manufacturing method
  • A kind of fce diode and its manufacturing method

Examples

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no. 1 example

[0050] image 3 It is a sectional view of the FCE diode of the first embodiment of the present invention, as image 3 As shown, it may include: a drift layer 301 , a P-type layer 302 , an N-buffer layer 303 , an N++ doped layer 304 and a P++ doped region 305 .

[0051] Specifically, the P-type layer 302 is located on the first surface of the drift layer 301 . The N-buffer layer 303 is located on the second surface of the drift layer 301 . The N++ doped layer 304 is formed by implanting N-type ions into the N-buffer layer 303 , wherein the thickness of the N++ doped layer 304 is smaller than that of the N-buffer layer 303 .

[0052] The N++ doped layer 304 is etched to form a plurality of N++ doped regions 3041 and trenches 3042 between every two adjacent N++ doped regions 3041 . The bottom 10 of the trench 3042 is in contact with the N-buffer layer 303 , that is, the bottom 10 of the trench 3042 exposes the part of the N-buffer layer 303 that has not been implanted with N-typ...

no. 2 example

[0057] Figure 4 It is a flow chart of the manufacturing method of the FCE diode of the second embodiment of the present invention, such as Figure 4 As shown, the following steps S410 to S450 may be included.

[0058] In step S410 , a P-type layer 302 is formed on the first surface of the drift layer 301 . The doping dose of the P-type layer 302 can be 10 12 cm -2 to 10 13 cm -2 , the junction depth is 2 to 10um.

[0059] In step S420, a layer of N-buffer layer 303 is formed on the second surface of the drift layer 301 to obtain the following Figure 5 Wafer shown. The doping dose of the N-buffer layer 303 can be 10 13 cm -2 to 10 14 cm -2 , the junction depth is 5 to 20um.

[0060] In step S430, to such as Figure 5 The shown N-buffer layer 303 is implanted with N-type ions to form an N++ doped layer 304, wherein the thickness of the N++ doped layer 304 is less than the thickness of the N-buffer layer 303, resulting in the following Figure 6 Wafer shown. The ...

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Abstract

The invention discloses an FCE diode and a manufacturing method thereof. The FCE diode comprises: a drift layer; a P-type layer positioned on a first surface of the drift layer; an N-buffer layer positioned on a second surface of the drift layer; an N++ layer formed by implanting N-type ions into the N-buffer layer A doped layer, wherein the thickness of the N++ doped layer is less than the thickness of the N buffer layer; a plurality of N++ doped regions formed by etching the N++ doped layer and the trench between every two adjacent N++ doped regions , the bottom 10 of the groove contacts the N-buffer layer; the P++ doped region that is not in contact with the N++ doped region formed by implanting P-type ions into the N-buffer layer through the groove, wherein the thickness of the P++ doped region is less than N‑buffer thickness. Adopting the present invention can improve the contact effect of the P++ doped region while ensuring better soft recovery characteristics, thereby simultaneously reducing the contact resistance of the cathode surface of the FCE diode.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to an FCE diode and a manufacturing method thereof. Background technique [0002] Existing FRD (Fast recovery diode, fast recovery diode) such as figure 1 As shown, it includes a drift layer 101, a P-type layer 102 on the first surface of the drift layer 101, an N-buffer layer 103 on the second surface of the drift layer 101, and N-type ions are implanted into the N-buffer layer 103. And the formed N++ doped layer 104, the first metal layer 105 on the P-type layer 102 and the second metal layer 106 on the N++ doped layer 104, wherein the thickness of the N++ doped layer 104 is smaller than the N-buffer layer 103 thickness of. [0003] An ideal FRD must have the characteristics of low conduction voltage drop, low reverse recovery loss and high soft recovery factor. However, for figure 1 As shown in the FRD, if it has low turn-on voltage drop characteristics, it is r...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/06H01L29/861H01L21/329
Inventor 刘国友朱利恒戴小平罗海辉黄建伟
Owner ZHUZHOU CRRC TIMES SEMICON CO LTD