Semiconductor device and forming method thereof

Abstract

The invention discloses a semiconductor device and a forming method thereof, and the method comprises the following steps: providing a semiconductor substrate, and forming protruding fin parts on thesurface of the semiconductor substrate; forming a gate dielectric layer on the surfaces of the fin parts; forming a gate structure crossing the fin parts on the semiconductor substrate; carrying out ion implantation on the gate dielectric layer so as to form doped dielectric layers in the gate dielectric layer at two sides of the gate structure; etching the fin parts on the two sides of the grid electrode structure to form replacement grooves in the fin parts, reserving the doped dielectric layer between the replacement grooves and the grid electrode structure, and enabling the etching rate ofthe etching to the doped dielectric layer to be lower than that of the etching to the grid dielectric layer; and forming a source-drain doped region in the replacement groove. According to the scheme, the source-drain doped region and the gate structure can be effectively separated, and the performance of the semiconductor device is improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device and a forming method thereof. Background technique [0002] Fin Field Effect Transistor (FinFET) is an emerging multi-gate device, which usually includes a fin protruding from the surface of the semiconductor substrate, a gate structure covering part of the top surface and sidewall of the fin, located at the gate Source and drain doped regions in the fins on both sides of the structure. [0003] Specifically, before forming the gate structure, a gate dielectric layer is usually formed on the surface of the fin to protect the fin and prevent leakage current between the source-drain doped region and the gate structure. [0004] However, in the prior art, when the source-drain doped region is formed, various processes such as etching and cleaning will affect the gate dielectric layer, and in severe cases, a short circuit will occur between the sourc...

AI Technical Summary

Problems solved by technology

[0004] However, in the prior art, when the source-drain doped region is formed, various processes such as etching and cleaning will affect the gate dielectric layer, and in severe cases, a short circuit will occur between the source-drain doped region and the gate structure. , resulting in leakage

Images