Full-isolation structure 9-tube SRAM memory cell and read-write operation method thereof

Abstract

The invention discloses a full-isolation structure 9-tube SRAM storage unit and a read-write operation method thereof, and the storage unit is additionally provided with a read path isolation tube onthe basis of a traditional 6-tube SRAM storage unit, adopts independent read bit lines and write bit lines to realize read-write path separation, and is additionally provided with a write path columngating tube and a read path column gating tube. As the column word lines are added to accurately control the accessed memory cells, the read-write process does not influence other memory cells which do not need to be accessed, and as the read isolation tubes and the special read bit lines and write bit lines are added, the high-noise tolerance design can be realized; due to the fact that the noisemargin of the storage unit is improved, the sensitivity of the circuit to power voltage changes is reduced, the storage state is more stable, and low-voltage operation can be achieved. As the read-write access is accurate to the corresponding storage unit, the whole-line work in the existing SRAM circuit architecture is not needed, and the dynamic power consumption of the circuit can be effectively reduced.

Description

technical field [0001] The invention belongs to the field of microelectronics, and relates to a 9-tube SRAM storage unit with a fully isolated structure and a read-write operation method thereof. Background technique [0002] With the continuous reduction of the process feature size and the continuous reduction of the working voltage, the anti-disturbance ability of the SRAM storage unit is getting weaker and weaker. In the existing SRAM design, 6 transistor (6transistor, 6T) storage units are generally used, such as figure 1 As shown, the storage unit has the advantages of compact structure, low power consumption, and good stability. A classic 6T memory cell consists of a cross-coupled pair of inverters and two access transistors. The gate of the access transistor is connected to the word line, and the drain / source is connected to the bit line. Word lines are used to select cells and bit lines are used to perform read or write operations on the cells. One side of the uni...

AI Technical Summary

Problems solved by technology

The shortcoming of this memory cell is: 1, because of having increased column word line CWL, can all turn off the negative feedback of the whole column memory cell of the row that will be written in cell when writing, thereby make this row not write target cell 2. During writing and reading, the bit line BL and the bit line reverse BL_ of the memory cell in the entire row where the target cell of the memory array is located are both discharging, and there is Large write and read power consumption

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