Reverse conduction insulation gate bipolar transistor structure and preparation method thereof
A bipolar transistor, insulated gate technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of reducing device reliability, low on-resistance, aggravating local current accumulation, etc., to achieve the turn-on voltage The effect of suppressing the foldback phenomenon, improving the distribution uniformity, and increasing the processing cost
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Embodiment 1
[0048] Figure 4 It is a schematic diagram of the cell cross-sectional structure of the RC-IGBT device 002 according to the first embodiment of the present invention. The composition of the device 002 includes: a collector (222) is located at the bottom of the device; more than one p + Collector region (206) and n + Cathode regions (207) are staggered on the collector electrodes (222); an n-type field stop layer (205) is located on the p + Collector region (206) and n + above the cathode region (207); a n - type drift region (201) is located on the n-type field stop layer (205); more than one groove (210) arranged in parallel from n - The upper surface of the type drift region (201) extends into n - type drift region (201); a gate electrode (223) is formed in a trench (210), and the gate electrode (223) is isolated from the inner wall of the corresponding trench (210) by a gate dielectric layer (211) ; A p-type body region (202) is located in n - above the drift region ...
Embodiment 2
[0062] Figure 15 It is a schematic diagram of the cell cross-sectional structure of the RC-IGBT device 003 according to the second embodiment of the present invention. Compared with the device 002 of the first embodiment of the present invention, the device 003 also has the following characteristics: the n - Buffer layer (208) and the n below it + There is a gap between the cathode regions (207), preferably, the size of the gap can be 0.2-0.5 microns. By setting the interval, it is possible to further avoid electric field punch-through to p + The collector region (206) problem maintains the breakdown voltage of the device from being affected. For the manufacturing method of device 003, the distance can be increased by Figure 12 The energy of p-type ion implantation shown in .
Embodiment 3
[0064] Figure 16 It is a schematic diagram of the cell cross-sectional structure of the RC-IGBT device 004 according to the third embodiment of the present invention. Compared with the device 002 of the first embodiment of the present invention, the device 004 also has the following characteristics: the n - Type buffer layer (208) is also provided with p - type buffer layer (209), preferably, the p - The peak doping concentration of the type buffer layer (209) is at 1e 15 cm -3 ~5e 15 cm -3 . due to p - Type buffer layer (209) behaves as a potential barrier for electrons, through the n - Add p in the buffer layer (208) - The type buffer layer (209) can further increase the resistance of the electron current on this path, thereby more effectively suppressing the turn-on voltage foldback problem. For the manufacturing method of device 004, the p - Type buffer layer (209) can be added by increasing Figure 12 The dose of p-type ion implantation shown in .
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