An integrated test system and method for an FPGA high-speed SerDes interface

Abstract

The invention discloses an integrated test system and method for an FPGA high-speed SerDes interface. The system comprises a central processing module, a switch and a digital programmable power supply, a code pattern generator, a test instrument module and a SerDes interface testing PCB. According to the invention, by adopting an integrated and separated special tester instrument, and testing thePCB hardware platform by carrying a SerDes interface, the remote control and integration of a test instrument are realized in the central processing module, meanwhile, the required parameters are tested and recorded, and the test records are output on the central processing module in a centralized manner, so that the full-coverage test of SerDes chip parameters is realized, the manual test intervention is reduced, the manual switching and the operation time are shortened, and the test efficiency of the FPGA chip SerDes interface is greatly improved.

Description

technical field [0001] The invention relates to the technical field of FPGA test fixtures, in particular to an integrated test system and method for an FPGA high-speed SerDes interface. Background technique [0002] SerDes is the abbreviation of serializer (serializer) / deserializer (deserializer). SerDes technology converts low-speed parallel data signals into high-speed serial data signals, and converts high-speed serial data signals into low-speed parallel signals to realize data. High speed transmission. [0003] At present, due to its high transmission rate and low cost, SerDes technology has become a common and important serial communication method. Among them, SerDes technology has been widely used in the field of I / O communication, SRIO, RapidIO and PCI- The physical layer of high-speed interfaces such as Express also uses SerDes interfaces. With the rapid development of SerDes technology, the high-speed serial port based on SerDes technology is gradually becoming...

AI Technical Summary

Problems solved by technology

At present, the functional testing of conventional resources (CLB, BRAM, DSP, IO, etc.) in the FPGA chip is usually carried out by the conventional ATE test method in the industry. For batch and large-scale testing, time-consuming, because ATE test equipment is mainly used for functional testing, its performance parameters cannot meet the testing requirements of the full frequency range covering SerDes interface parameters

In the stage of chip trial production, ATE testing cannot meet the needs of rapid testing of high-speed SerDes modules. If a separate special test instrument is used for thorough testing at this stage, the SerDes interface can be tested in the entire frequency band. There are a series of problems such as long test time and high test cost

Images