Semiconductor structures and methods of forming them

A semiconductor and gate structure technology, applied in the field of semiconductor structure and its formation, can solve problems such as poor performance of vertical nanowire transistors, and achieve the effects of high integration and reduced energy consumption

Active Publication Date: 2021-06-08
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, the performance of existing vertical nanowire transistors is poor

Method used

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  • Semiconductor structures and methods of forming them
  • Semiconductor structures and methods of forming them
  • Semiconductor structures and methods of forming them

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Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0038] There are many problems in the semiconductor structure in the prior art, for example, the performance of the semiconductor structure is poor.

[0039] Now in combination with a semiconductor structure, the reasons for the poor performance of the semiconductor structure are analyzed:

[0040] Due to the large substrate surface occupied by conventional planar transistors, the integration degree of the semiconductor structure is low. In order to increase the integration degree of the formed semiconductor structure, a vertical nanowire transistor is proposed.

[0041] figure 1 and figure 2 It is a structural schematic diagram of each step of a method for forming a vertical nanowire transistor.

[0042] Please refer to figure 1 , a substrate 130 is provided, the surface of the substrate 130 has a fin post 131, and the fin post 131 includes a bottom region I, a channel region II on the bottom region I, and a top portion on the channel region II Zone III.

[0043] conti...

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Abstract

A semiconductor structure and a method for forming the same, wherein the forming method includes: providing a substrate with a fin column on the substrate, the fin column includes a bottom region, a channel region located on the bottom region, and a channel region located on the bottom region. A top region on the channel region; a first isolation layer is formed on the substrate, and the first isolation layer covers the bottom region of the fin column; and a sidewall surface of the channel region of the fin column is formed a first gate oxide layer and a second gate oxide layer, the second gate oxide layer is located on the top surface of the first gate oxide layer, and the thicknesses of the first gate oxide layer and the second gate oxide layer are different; A gate structure is formed on the top surface of the first isolation layer, and the gate structure covers the first gate oxide layer and the second gate oxide layer; a second isolation layer is formed on the top surface of the gate structure, and the second An isolation layer covers sidewalls of the top region of the fin post. The formation method can improve the performance of the semiconductor structure.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration. With the improvement of component density and integration of semiconductor devices, the size of transistors is getting smaller and smaller, and the reduction of transistor size makes the short channel effect more and more significant. [0003] In order to reduce the short channel effect, the fin field effect transistor was born. The gate of the FinFET has a forked 3D structure similar to a fish fin. The gate of the fin field effect transistor can control the switching on and off of the circuit on multiple sides of the fin column, so that the short channel effect of the transistor can be well suppressed. [0004]...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8234H01L27/088
CPCH01L21/823431H01L21/823462H01L21/823481H01L21/823487H01L27/0886
Inventor 张焕云吴健
Owner SEMICON MFG INT (SHANGHAI) CORP
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