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A time-to-digital converter system and multiple delay phase-locked loop including the system

A delay-locked loop, time-to-digital technology, applied in time-to-digital converter, analog/digital conversion, analog conversion, etc., can solve the problem of in-band quantization noise determination, etc., to improve spurs, reduce quantization noise, and reduce consumption The effect of power

Active Publication Date: 2020-05-22
FUDAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the disadvantage of using a digital multiple DLL is that its in-band quantization noise is determined by the time-to-digital converter

Method used

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  • A time-to-digital converter system and multiple delay phase-locked loop including the system
  • A time-to-digital converter system and multiple delay phase-locked loop including the system

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Embodiment Construction

[0020] The present invention will be further described below through specific embodiments in conjunction with the accompanying drawings. These embodiments are only used to illustrate the present invention, and are not intended to limit the protection scope of the present invention.

[0021] The present invention is a time-to-digital conversion system applied to a multiple delay phase-locked loop, mainly to realize innovation on the invention framework, and the time-to-digital converter, digital-to-time converter, time amplifier, digital-to-analog converter, successive approximation used in the present invention Register-type analog-to-digital converters and shifters are also commonly used circuit architectures. The two main circuits are time-to-digital converters and digital-to-time converters. The core architecture of time-to-digital converters is commonly used high-speed time-to-digital converters. , the digital time converter is mainly composed of a delay chain and a data se...

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Abstract

The invention discloses a time-to-digital converter system and a multiple delay phase-locked loop comprising the same. The system comprises a first-level time-to-digital converter, a first-level digital-to-time converter, a first-level time amplifier, a second-level time-to-digital converter, a second-level digital-to-time converter, a second-level time amplifier, a third-level successive approximation register type analog-to-digital converter and a digital-to-analog-to-digital converter. The time-to-digital converter system provided by the invention and the multiple delay phase-locked loop capable of lowering in-band quantization noise use a cascade algorithm similar to Delta-Sigma, the accuracy of the time-to-digital converter applied to the multiple delay phase-locked loop is effectively improved, the quantization noise is lowered, and the generation of the stray of the multiple delay phase-locked loop is eliminated.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a time-to-digital converter system and a multiple delay phase-locked loop comprising the system. Background technique [0002] With the advancement of technology, in the application of all-digital chips, in order to convert the off-chip low-frequency oscillator input signal into a high-frequency clock signal, the use of on-chip frequency multiplier clock has occupied an important position. In order to obtain a stable high-frequency clock signal that is not affected by phase noise, the multiple delay phase-locked loop must have the function of suppressing phase noise. In addition, with the rise of handheld devices, low power consumption has become an indispensable condition in order to prolong the battery life of the handheld devices. [0003] In the multiple delay phase-locked loop, the voltage-controlled oscillator is a loop loop, so the jitter generated by the volt...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M1/50
CPCG04F10/005H03L7/081H03L7/099H03L7/18H03M3/344
Inventor 屠于婷叶大蔚史传进
Owner FUDAN UNIV
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