Group iii-nitride semiconductor substrate, and method for manufacturing group iii-nitride semiconductor substrate

A technology of nitride semiconductors and manufacturing methods, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, chemical instruments and methods, etc., and can solve the problems of internal quantum efficiency reduction and other issues

Pending Publication Date: 2019-08-23
FURUKAWA COMPANY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As disclosed in Patent Document 1, when a device (such as an optical device, an electronic device, etc.) is formed on the c-plane of a group III nitride semiconductor crystal, the piezoelectric field causes a decrease in the internal quantum efficiency

Method used

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  • Group iii-nitride semiconductor substrate, and method for manufacturing group iii-nitride semiconductor substrate
  • Group iii-nitride semiconductor substrate, and method for manufacturing group iii-nitride semiconductor substrate
  • Group iii-nitride semiconductor substrate, and method for manufacturing group iii-nitride semiconductor substrate

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no. 1 approach ＞

[0032] First, an example of a method for manufacturing a group III nitride semiconductor substrate according to this embodiment will be described. figure 1 It is a flowchart showing an example of the process flow of the method for manufacturing a group III nitride semiconductor substrate according to the present embodiment. As shown in the figure, the method for manufacturing a group III nitride semiconductor substrate according to this embodiment includes a sapphire substrate preparation step S10 , a heat treatment step S20 , a buffer layer forming step S30 , and a growth step S40 .

[0033] In the sapphire substrate preparation step S10 , a sapphire substrate having a {10-10} plane or a {10-10} plane as a main surface inclined at a predetermined angle in a predetermined direction is prepared. figure 2 (1) shows an example of a schematic side view of the sapphire substrate 10 prepared in this step. The diameter of the sapphire substrate 10 is, for example, 1 inch or more. ...

no. 1 example ＞

[0138] Various sapphire substrates 10 are prepared for the plane orientation (first factor) of the plurality of main surfaces 11 . The sapphire substrate 10 has a thickness of 430 μm and a diameter of 2 inches.

[0139] Next, each prepared sapphire substrate 10 was heat-treated under the following conditions.

[0140] Temperature: 950℃~1100℃.

[0141] Pressure: 200torr.

[0142] Heat treatment time: 10 minutes or 15 minutes.

[0143] Carrier gas: H 2 , N 2 .

[0144] h 2 (Carrier gas) supply volume: 4.0slm~9.0slm.

[0145] N 2 (Carrier gas) supply volume: 1.5slm.

[0146] In addition, samples were produced in which the presence or absence (second factor) of nitriding treatment during heat treatment was different. Specifically, two types of samples were produced: NH 3 Samples subjected to nitriding treatment and NH not supplied during heat treatment 3 Samples without nitriding treatment.

[0147] After the heat treatment, a buffer layer 20 (AlN buffer layer) having...

no. 2 approach ＞

[0184] Figure 5 It is a flowchart showing an example of the process flow of the method for manufacturing a group III nitride semiconductor substrate according to the present embodiment. As shown in the figure, the method for manufacturing a III-nitride semiconductor substrate according to this embodiment includes a sapphire substrate preparation step S10, a heat treatment step S20, a preflow step S25, a buffer layer formation step S30, and a growth step S40. A removal step S50 may also be included. According to the present embodiment, the group III nitride semiconductor layer 30 can be formed by epitaxially growing the group III nitride semiconductor with the desired semipolar plane on the N polarity side as the growth plane. Next, each step will be described.

[0185] The sapphire substrate preparation step S10 is the same as that of the first embodiment.

[0186]In the heat treatment step S20 , the sapphire substrate 10 is heat-treated while performing the nitriding trea...

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Abstract

Provided is a method for manufacturing a group III-nitride semiconductor substrate, the method comprising: a sapphire substrate preparation step S10 of preparing a sapphire substrate that has, as a principal surface, a {10-10} plane or a surface tilted a predetermined angle in a predetermined direction from the {10-10} plane; a heat treatment step S20 of heat treating the sapphire substrate whileperforming or not performing a nitriding treatment; a buffer layer forming step S30 of forming a buffer layer on the principal surface of the sapphire substrate after the heat treatment; and a growingstep S40 of forming, on the buffer layer, a group III-nitride semiconductor layer having a growth surface oriented in a predetermined plane direction, wherein at least one among the plane direction of the principal surface of the sapphire substrate, whether or not to perform the nitriding treatment during the heat treatment, and the growth temperature in the buffer layer forming step is adjustedso that the growth surface of the group III-nitride semiconductor layer is oriented in the predetermined plane direction.

Description

technical field [0001] The invention relates to a group III nitride semiconductor substrate and a method for manufacturing the group III nitride semiconductor substrate. Background technique [0002] The related art is disclosed in Patent Document 1. As disclosed in Patent Document 1, when a device (for example, an optical device, an electronic device, etc.) is formed on the c-plane of a group III nitride semiconductor crystal, a piezoelectric field causes a decrease in internal quantum efficiency. Therefore, attempts have been made to form devices on so-called semipolar planes (different planes from polar and nonpolar planes). [0003] prior art literature [0004] patent documents [0005] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2012-160755. Contents of the invention [0006] The problem to be solved by the invention [0007] If the device is formed on the semipolar plane, the internal quantum efficiency can be improved compared to ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/205C23C16/02C23C16/34C30B29/38H01L21/20
CPCH01L21/0242H01L21/0254H01L21/02458H01L21/02433H01L21/02658C30B29/403C30B25/10C30B25/186H01L21/02247H01L21/324H01L21/02389H01L21/67017H01L21/67098H01L21/67248C30B29/38C23C16/02C23C16/34H01L29/2003
Inventor 住田行常藤山泰治
Owner FURUKAWA COMPANY
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