Gallium nitride enhanced vertical transistor assembly and manufacturing method thereof
An enhanced, vertical technology, used in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., to solve problems such as the effect of surface defects on devices
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[0025] Below in conjunction with specific embodiment, further illustrate the present invention. It should be understood that these examples are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the teachings of the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms also fall within the scope defined by the appended claims of the present application.
[0026] A gallium nitride enhanced vertical transistor assembly provided by the present invention includes a gate structure, a source structure, a drain structure, an n-type doped region, a p-type doped region, an oxide and a gate dielectric layer.
[0027] Such as figure 1 As shown, the present invention includes drain layer 10, conductive substrate layer 1, n + GaN layer 2, n-type GaN layer 3, p-type GaN layer 4 and n + GaN...
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