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Gallium nitride enhanced vertical transistor assembly and manufacturing method thereof

An enhanced, vertical technology, used in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., to solve problems such as the effect of surface defects on devices

Pending Publication Date: 2019-10-25
SHANGHAI TECH UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, such HEMT devices are usually depletion-type devices, which require a negative voltage to deplete the electronic channel and turn off the device; in addition, the breakdown voltage of this lateral device structure is proportional to the transistor area, and the material interface is exposed on the sample surface, making the device susceptible to surface defects

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  • Gallium nitride enhanced vertical transistor assembly and manufacturing method thereof
  • Gallium nitride enhanced vertical transistor assembly and manufacturing method thereof
  • Gallium nitride enhanced vertical transistor assembly and manufacturing method thereof

Examples

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Embodiment Construction

[0025] Below in conjunction with specific embodiment, further illustrate the present invention. It should be understood that these examples are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the teachings of the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms also fall within the scope defined by the appended claims of the present application.

[0026] A gallium nitride enhanced vertical transistor assembly provided by the present invention includes a gate structure, a source structure, a drain structure, an n-type doped region, a p-type doped region, an oxide and a gate dielectric layer.

[0027] Such as figure 1 As shown, the present invention includes drain layer 10, conductive substrate layer 1, n + GaN layer 2, n-type GaN layer 3, p-type GaN layer 4 and n + GaN...

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Abstract

The invention provides a gallium nitride enhanced vertical transistor assembly. The assembly is characterized by comprising a drain layer, a conductive substrate layer, an n+ GaN layer, an n-type GaNlayer, a p-type GaN layer and an n+ GaN layer which are sequentially disposed from bottom to top respectively. The invention further provides a manufacturing method of the gallium nitride enhanced vertical transistor assembly. The assembly is advantaged in that due to the micro-nano columnar structure, the npn-type layers in the columnar structure respectively have a sufficient surface area / volumeratio, the annealing process is utilized to facilitate to activate Mg doping in a p-type gallium nitride semiconductor, the sufficient hole concentration is achieved, an enhanced device which is notconducted in a balanced state and is conducted under a forward turn-on voltage is achieved, a disadvantage that the p-type gallium nitride semiconductor in a film device is not easily activated afterbeing covered by the n-type semiconductor is effectively solved, secondly, a turn-on threshold voltage can be regulated by changing the size of the device, and needs of different applications are satisfied.

Description

technical field [0001] The invention relates to a columnar micro-nano device and a manufacturing method thereof, in particular to a gallium nitride enhanced vertical transistor component and a manufacturing method thereof. Background technique [0002] Gallium nitride has a band gap of 3.4eV, a breakdown field strength of more than 3MV / cm, and an electron mobility of more than 1000cm 2 The nature of / V·s. At present, high electron mobility transistors (HEMTs) based on AlGaN / GaN heterojunctions use spontaneous polarization and piezoelectric polarization effects to form a two-dimensional electron gas at the interface. However, such HEMT devices are usually depletion-type devices, which require a negative voltage to deplete the electronic channel and turn off the device; in addition, the breakdown voltage of this lateral device structure is proportional to the transistor area, and the material interface is exposed on the sample surface, making such devices susceptible to surf...

Claims

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Application Information

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IPC IPC(8): H01L29/06H01L29/778H01L21/335
CPCH01L29/7788H01L29/66462H01L29/0657H01L29/0684
Inventor 张羽邹新波杨杨
Owner SHANGHAI TECH UNIV