Manufacturing method of the zeroth layer interlayer film

Abstract

The invention discloses a method for manufacturing the zeroth layer interlayer film, comprising steps: step 1, forming a first grid structure on the surface of a semiconductor substrate; the area between each first grid structure is a spacer area; forming side wall and form a contact hole etch stop layer composed of a nitride film; Step 2, grow the zeroth interlayer film; Step 3, perform the first selective chemical mechanical polishing to grind and stop the zeroth interlayer film On the contact hole etching stop layer on the top surface of the sidewall; step 4, perform the second non-selective chemical mechanical polishing to simultaneously polish the oxide film and the nitride film and stop the contact hole etching on the top surface of the polysilicon gate on the etch stop layer; Step 5, performing a third selective etching to remove the remaining contact hole etch stop layer on the top surface of the polysilicon gate. The invention can eliminate the butterfly defect of the zeroth interlayer film and improve the product yield.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a method for manufacturing the zeroth interlayer film. Background technique [0002] In the current advanced logic chip technology, multiple device units are integrated on the same semiconductor substrate wafer. The gate structure of the device unit includes polysilicon gates. The spacing of each polysilicon gate is not exactly the same, but has a variety of spacing values. The space between the polysilicon gates often needs to be filled with the zeroth interlayer film (ILD0). When the growth of the zeroth interlayer film is completed, it will also extend to the top region of the polysilicon gate outside the spacer, and then chemical mechanical polishing (CMP) is required to remove the zeroth interlayer film on the top region of the polysilicon gate outside the spacer and polishing the zeroth interlayer film of the spacer to be level with the top s...

AI Technical Summary

Problems solved by technology

And if more grinding is done in order to ensure that there is no metal residue, it is easy to grind the silicon germanium layer 106 at the bottom, which will also cause electrical abnormalities of the device

Images