Substrate, chip package structure and preparation method thereof

Abstract

The present application discloses a substrate, a chip packaging structure and a preparation method thereof. The substrate includes a substrate body, the substrate body includes a filling glue setting area, the substrate body is provided with a solder resist layer, and the solder resist layer is surrounded by At least one groove is provided in the setting area of ​​the filling glue, and the groove acts as a buffer barrier layer for overflowing glue, so that the ability of overflowing glue can be reduced to below 0.4mm. The depth of the groove is less than or equal to the depth of the solder resist layer, which will not damage the copper skin under the solder resist layer, so it will not affect the electrical performance, and indirectly reduce the size required for packaging the chip, and provide a solution for other components. The arrangement of devices provides more space. The production of the groove can be completed when the solder mask is produced on the substrate without additional treatment, the process is simple, the cost is low, the mass production is easy, and the practicability is strong.

Description

technical field [0001] The present application generally relates to the technical field of semiconductor manufacturing, and specifically relates to a substrate, a chip packaging structure and a preparation method thereof. Background technique [0002] In the flip-chip underfill process, controlling the overflow width of the bottom encapsulant often affects the package layout, and a smaller overflow width helps to reduce the package size and provide sufficient space for the layout of other components. The existing control methods are mainly through optimizing the dispensing process parameters, improving the formulation of the bottom packaging glue, and using non-conductive film filling (NCF) and other methods. However, there are always limitations in the improvement of process parameters and excellent glue formulations, and it is difficult to precisely control them. The best process capability that has been achieved so far is 1.5mm-2mm. However, the use of non-conductive fi...

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Problems solved by technology

However, the use of non-conductive film underfill is costly and low in production efficiency, and a pressure oven is required in the process to solve the problem of voids, which greatly increases production costs

[0003] The Chinese patent with the publication number CN108281409A published on July 13, 2018 discloses that a Teflon hydrophobic layer is sprayed on the surface of the substrate through a precision micro-valve and then sintered at a high temperature to form a raised glue overflow suppression layer. The thickness of the suppression layer is 0.1-0.3mm, the width of the suppression layer is 0.1-0.4mm; this scheme introduces new organic materials, requires ultra-high temperature sintering, and has pollution and process control problems

The material width is 0.1mm-0.4mm, and the thickness is 0.1-0.3mm. The process window is large, and the thickness may exceed the chip thickness. It is not suitable for large-size ultra-thin chips.

The Chinese patent with the publication number CN206441716U published on August 25, 2017 discloses that a glue storage tank is designed on the substrate. Although this solution does not have pollution and process control problems, laser opening of rectangular grooves on the surface of the substrate is suitable for ultra-high-density GPUs. For wiring products, the slotting of the substrate will affect the effect of wiring and electrical performance, and the solder mask layer and the copper skin slotting need different laser process control, the production cost is high, and the practicability is not strong

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