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A kind of transistor device enhancement mode and depletion mode gate integrated fabrication method and device

A manufacturing method and depletion-type technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of limited process selection and difficult development, and achieve the effect of rich selectivity and robust protection

Active Publication Date: 2021-11-19
福建省福联集成电路有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] For this reason, it is necessary to provide a transistor device enhancement-type and depletion-type gate integrated manufacturing method and device to solve the problems of limited process selection and difficult development in the existing transistor device manufacturing process

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  • A kind of transistor device enhancement mode and depletion mode gate integrated fabrication method and device
  • A kind of transistor device enhancement mode and depletion mode gate integrated fabrication method and device
  • A kind of transistor device enhancement mode and depletion mode gate integrated fabrication method and device

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Embodiment Construction

[0030] In order to explain in detail the technical content, structural features, achieved goals and effects of the technical solution, the following will be described in detail in conjunction with specific embodiments and accompanying drawings.

[0031] see Figure 1 to Figure 5 , the present embodiment provides an integrated manufacturing method for the enhanced gate and the depleted gate of the transistor device, and the manufacturing process of the present invention can be performed on a gallium arsenide wafer. First of all, the enhanced gate must be fabricated, generally the bottom photoresist of the enhanced gate is fabricated, and then the bottom opening of the enhanced gate is completed by exposure and development, and then the top photoresist of the enhanced gate is fabricated, and then Exposure and development complete the top opening of the enhanced gate, and then deposit metal for the first time to complete the fabrication of the enhanced gate, and then proceed to f...

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Abstract

The invention discloses a transistor device enhanced and depleted gate integrated manufacturing method and device, wherein the method includes the following steps: depositing a protective layer on the device surface of the enhanced gate; coating photoresist, and depleting Develop openings at the position of the depletion gate, and the opening is a trapezoidal window; use photoresist as a mask to etch the protective layer at the position of the depletion gate; continue to etch the cap layer at the position of the depletion gate; evaporate metal, deposit metal to the depletion gate location to form the depletion gate. The present invention can immediately protect the device by depositing a protective layer after the fabrication of the enhanced gate, prevent the gate from being affected by external factors such as particles, oxides, and hydrogen, and protect the robustness of the gate metal. Then, when making the depletion gate, the pattern inversion technology of the positive photoresist can be used, which enriches the selectivity of the process. Avoid the problems of poor photoresist adhesion and photoresist peeling off after etching, which are faced by negative photoresist.

Description

technical field [0001] The invention relates to the field of manufacturing semiconductor devices, in particular to an integrated manufacturing method and device for enhanced and depleted gates of transistor devices. Background technique [0002] In the PHEMT (pseudo-modulation doped heterojunction field-effect transistor) device integrated enhancement mode and depletion mode process, the first layer of metal is fabricated, and then the enhanced gate is fabricated, and then photoresist is used to coat Glue, exposure, development, supplemented by metal evaporation and other processes to complete the manufacture of the depletion gate. Existing technology has following shortcoming: [0003] Disadvantage 1: Only negative photoresist can be used, positive photoresist cannot be used, and the pattern inversion technology of positive photoresist cannot be used, and the process options are very limited. [0004] Disadvantage 2: Negative photoresist has low resolution and poor adhesi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/027H01L21/28H01L21/335
CPCH01L21/0274H01L29/401H01L29/66462
Inventor 郑育新詹智梅陈东仰肖俊鹏林豪王潮斌林张鸿林伟铭
Owner 福建省福联集成电路有限公司