Method and system for repairing time sequence violations in chip design

Abstract

The invention discloses a method and system for repairing time sequence violations in chip design, and relates to the technical field of integrated circuit design. The method comprises the following steps of selecting a target repair path from time sequence violation paths, grabbing all basic units and the delay values corresponding to the basic units in the target repair path and sorting, and sequentially selecting the basic units as the target units according to the sequence; judging whether the violation is an establishment time violation or a retention time violation, replacing the targetunits sequentially based on the rules which do not affect other time sequence paths, and obtaining the repair operation meeting requirements; and converting the repair operation into an operation command which can be identified by a layout wiring tool, executing the operation on the layout wiring tool, and ending the repair under the condition of verifying that the time sequence analysis result after the operation meets the time sequence requirement. According to the invention, when the time sequence violation repair is carried out, the re-layout and the re-wiring are not needed, and the timesequence convergence can be realized through the rapid iteration.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, in particular to a method for repairing timing violations in chip design. Background technique [0002] In the design of integrated circuit chips, the main factors that determine the operating speed and design area of ​​integrated circuit chips are as follows: production process, code writing style, physical implementation process from code to layout, etc. Fixing timing is one of the most important critical steps in the code-to-layout physical implementation process. With the development of deep sub-meter technology, the design process of the chip is getting smaller and smaller, the delay of the connection between the device and the device is becoming more and more unstable, the scale of the chip design is getting bigger and bigger, and the design frequency is getting higher and higher. . Various factors lead to increasingly difficult chip timing convergence. The timing conve...

AI Technical Summary

Problems solved by technology

[0005] 1) If additional protection time is added to the timing path that has already met the design requirements, layout and wiring will result in the addition of a large number of redundant basic units in the timing path, increasing the area of ​​the chip and increasing the design cost

[0006] 2) For the timing path that does not meet the design requirements, if additional guard time is added to place and route again, because the tools used in the placement and routing stage and the timing analysis stage are different, it may also occur that a certain timing path meets the requirements in the placement and routing tool. The design requirements but the timing analysis tool analyzes the problem that does not meet the design requirements, and repeated iterations of the same method will waste a lot of time

It not only lengthens the design cycle, but also cannot guarantee that the next layout and routing results will fully meet the timing analysis, which is a waste of time and lacks control over the results

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