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Method for generating filling graph of FDSOI standard unit and layout method

A standard cell and standard cell library technology, applied in the direction of electrical components, electrical solid devices, circuits, etc., can solve problems such as area waste and achieve the effect of reducing production costs

Active Publication Date: 2020-01-07
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The present application provides a method for generating a filling pattern of an FDSOI standard cell and a layout layout method, which can solve the problem of area waste caused by partitioning layout of different types of devices in the FDSOI layout structure provided in the related art

Method used

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  • Method for generating filling graph of FDSOI standard unit and layout method
  • Method for generating filling graph of FDSOI standard unit and layout method
  • Method for generating filling graph of FDSOI standard unit and layout method

Examples

Experimental program
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Embodiment 1

[0052] Image 6 It is a method for generating a filling pattern of an FDSOI standard cell provided in an exemplary embodiment of the present application. The method is applied to semiconductor manufacturing, and the method includes:

[0053] Step 601, acquire the parameters of the FDSOI standard cell in the standard cell library.

[0054] Among them, the parameters of the FDSOI standard cell include at least one of the height of the FDSOI standard cell, the N-type well (Well) edge, the well identification layer (Well-Reverse) edge, the horizontal wiring pitch and the vertical wiring pitch; the FDSOI standard cell includes RVT device, LVT device, SNW device, and SPW device at least two.

[0055] Step 602, determine the parameters of the filling unit according to the parameters of the FDSOI standard unit.

[0056] Among them, the filling unit is a structure arranged between FDSOI standard units; the parameters of the filling unit include the height of the filling unit, the N-t...

Embodiment 2

[0060] With reference to Example 1, the difference between Example 2 and Example 1 is: for "determining the parameters of the filling unit according to the parameters of the FDSOI standard unit" in step 602, it includes: determining the height of the filling unit as the height of the FDSOI standard unit .

[0061] That is, in this embodiment, the filling cell height is the same as the relative height of all FDSOI standard cells in the standard cell library, and the relative height is the height relative to the origin.

Embodiment 3

[0063] Referring to Embodiment 1 or Embodiment 2, the difference between Embodiment 3 and Embodiment 1 and Embodiment 2 is that: for "determining the parameters of the filling unit according to the parameters of the FDSOI standard unit" in step 602, it may also include: according to the FDSOI standard The N-type well edge of the cell defines the N-type well region that fills the cell.

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Abstract

The invention discloses a method for generating a filling graph of an FDSOI standard unit and a layout method. The method comprises steps of acquiring parameters of an FDSOI standard unit in a standard unit database; determining parameters of the filling unit according to the parameters of the FDSOI standard unit; generating the filling graph of the FDSOI standard unit according to the parametersof the filling unit. The method is advantaged in that the parameters of the filling unit are determined according to the parameters of the FDSOI standard unit, the filling graph of the FDSOI standardunit is generated according to the parameters of the filling unit, as the parameters of the filling unit are determined based on the parameters of the FDSOI standard unit, a splicing problem of different types of FDSOI devices can be solved, different types of FDSOI devices can be prepared on the same wafer, and production cost is reduced.

Description

technical field [0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a method for generating a filling pattern of an FDSOI standard cell and a layout method. Background technique [0002] Standard cell library, which includes layout library, symbol library, circuit logic library, etc., contains combinational logic, sequential logic, functional units and special type units, and is the basic part of the back-end design process of integrated circuit chips. The pre-designed standard cells in the standard cell library can be used for automatic logic synthesis and layout layout, which can greatly improve design efficiency. [0003] The fully depleted silicon on insulator (FDSOI) structure is a semiconductor structure in which transistors are placed on silicon insulator (SOI). The FDSOI structure adds an insulating material between the transistors, so that the parasitic capacitance between the two is large. The amplitud...

Claims

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Application Information

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IPC IPC(8): H01L27/02
CPCH01L27/0207
Inventor 张凯胡晓明
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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