Low-voltage crystal oscillator circuit compatible with GPIO

Abstract

Low voltage crystal oscillator having native NMOS transistors used for coupling / decoupling to / from GPIO. The native NMOS transistors function properly at a low supply voltage when on (low resistance)and a high supply voltage when off (high resistance). Oscillator Gm driver bias resistors are repurposed to degenerate the native NMOS transistors when they are off, thereby reducing the leakage current thereof (oscillator circuit decoupled from GPIO nodes). This ensures compliance with the CMOS IIH leakage current specification during an external clock (EC) mode at a high supply voltage.

Description

[0001] Related Patent Applications [0002] This application claims priority to commonly-owned US Provisional Patent Application No. 62 / 542,050, filed August 7, 2017; which Provisional Patent Application is hereby incorporated by reference herein for all purposes. technical field [0003] The present disclosure relates to oscillators, and in particular to low voltage crystal oscillator circuits that comply with Complementary Metal Oxide Semiconductor (CMOS) Input Leakage High (IIH) specifications for shared general purpose input output (GPIO) nodes. Background technique [0004] Operation of a low voltage crystal oscillator circuit coupled to a general purpose input output (GPIO) node, such as a connection pad of an integrated circuit (IC), is a desired feature in today's integrated circuit products. However, the low voltage operation of crystal oscillator circuits based on N-channel metal oxide semiconductor (NMOS) Gm drives is limited by the minimum Vdd (supply voltage ) ...

AI Technical Summary

Problems solved by technology

However, when the GPIO pads associated with the crystal oscillator circuit are in "external clock" mode and driven by CMOS logic, or in other uses of these GPIO pads, using native NMOS transistor switches will not be sufficient to isolate the oscillation Gm drives the transistor to prevent excessive current leakage through the

Therefore, the CMOS IIH leakage current specification cannot be met

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