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Storage chip fault-tolerant device based on LDPC codes and fault-tolerant error correction method

An LDPC code and memory chip technology, which is applied in the field of memory chip fault-tolerant devices and new-type memory chip fault-tolerant devices, can solve the problems of low error correction performance of memory chips, reduced access speed, low space utilization, etc., to improve data throughput. rate and access speed, improve reliability, reduce the effect of faulty platforms

Active Publication Date: 2020-02-04
XIAN TECHNOLOGICAL UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The present invention provides an LDPC code-based memory chip error-tolerant device and error-tolerant error correction method to overcome the problems of low error correction performance, long time delay, low space utilization rate, and high power consumption of the memory chip in the existing device, and at the same time overcome the current problems. There is a method that needs to be compiled and decoded every time the data storage unit is accessed, which also reduces the problem of access speed

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  • Storage chip fault-tolerant device based on LDPC codes and fault-tolerant error correction method
  • Storage chip fault-tolerant device based on LDPC codes and fault-tolerant error correction method
  • Storage chip fault-tolerant device based on LDPC codes and fault-tolerant error correction method

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Embodiment Construction

[0028] The present invention will be described in detail below with reference to the drawings and embodiments.

[0029] The technical idea given by the present invention is: (1) The device adopts TSV vertical vertical integration technology to form a three-dimensional stacked storage unit by using the normal data storage carrier wafer and the error correction control carrier wafer, and the error correction control wafer carries the fault tolerance verification Data and error correction control unit, and share the address, data and control bus of the normal data storage bank; (2) The method is that the error correction controller regularly reads normal data and error-tolerant data, and performs Two-bit bit flip translation based on LDPC code If the decoding is successful, the error correction data write-back operation will be performed, otherwise the decoding will end; (3) Read and write conflict detection will be performed, and if there is no conflict, the correct data after er...

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Abstract

The invention discloses a storage chip fault-tolerant device based on LDPC codes and a fault-tolerant error correction method. According to the technical scheme, a TSV longitudinal and vertical integration technology is adopted, a normal data storage carrier wafer and an error correction control carrier wafer form a three-dimensional stacked storage unit, and the error correction control wafer bears fault-tolerant check data and an error correction control unit and shares an address, data and a control bus of a normal data storage body; (2) the error correction controller reads normal data andfault-tolerant data at regular time, Twi-bit flipping decoding based on LDPC codes is carried out, if decoding succeeds, error correction data write-back operation is carried out, and if decoding does not succeed, decoding is ended; and (3) read-write conflict detection is made If no conflict exists, the correct data is written instantly after error correction back to the storage unit and the verification unit, otherwise, an avoidance strategy is satrtedand the data is successfully written back or the conflict detection fails. The invention has super-strong error correction capability, is convenient for electronic packaging, is easy for hardware implementation, and can be applied to the field of storage fault tolerance of high-speed Cache, flash memory, SSD and the like.

Description

technical field [0001] The invention relates to the technical field of computer fault tolerance, specifically discloses a fault tolerance device for a new memory chip, and in particular relates to a memory chip fault tolerance device and an error tolerance and correction method based on LDPC codes. Background technique [0002] In recent years, with the vigorous development of emerging information technology industries such as cloud computing, big data, Internet of Things, and mobile Internet, data storage, transmission, and processing are unprecedented in terms of speed and scale. According to statistics, the amount of newly generated information in the world doubles every three years. There is no doubt about the practical significance of how to store these data safely and reliably. Integrated circuit storage devices represented by new solid-state drives (SSD, Solid State Drive) have attracted close attention from industry and academia due to their durability, low power co...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/42G11C16/08
CPCG11C16/08G11C29/42
Inventor 郭军军王乐王正源
Owner XIAN TECHNOLOGICAL UNIV
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