Standard unit substrate-coupling capacitor layout structure based on FinFET technology

Abstract

The invention provides a standard unit substrate-coupling capacitor layout structure based on a FinFET technology. The standard unit substrate-coupling capacitor layout structure is composed of a first layout area, a second layout area, a third layout area and a fourth layout area, and comprises an active region, a fin layer, a metal 0 layer, a contact hole layer, a metal 1 layer, a metal 0 layercut-off layer, a polycrystalline silicon layer, a polycrystalline silicon edge defining layer and a polycrystalline silicon cut-off layer, wherein the polycrystalline silicon layer is a plurality of strip-shaped structures which are arranged at equal intervals, the overlapping area of the polycrystalline silicon layer and the active region in the first layout region, the second layout region, thethird layout region and the fourth layout region is attached and surrounded by the polycrystalline silicon edge defining layer. On the basis that the original layout area is not increased, the densityof the active region is increased, and the dual functions of the substrate and the coupling capacitor are achieved at the same time.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a standard unit substrate-coupling capacitor layout structure based on FinFET technology. Background technique [0002] Such as figure 1 as shown, figure 1 It is shown as a standard cell TAP (substrate) layout in the prior art. The entire cell layout is 12 Poly Pitch (the sum of polysilicon line width and spacing) width, and the layout is divided into a first layout area and a second layout area. Wherein, the first layout area is NTAP (N-type substrate), and the second layout area is PTAP (P-type substrate). This layout can only realize the TAP (substrate) function alone, and the active area arrangement density (AA density) is low, which is prone to problems. [0003] Therefore, it is necessary to propose a new standard cell substrate-coupling capacitor layout structure based on FinFET technology to solve the above-mentioned problems of single function and low arrang...

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Problems solved by technology

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a standard cell substrate-coupling capacitor layout structure based on FinFET technology, which is used to solve the problem that can only be realized in the standard cell substrate layout structure in the prior art. A single substrate function, and the active area is densely arranged

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