Clock circuit and clock signal generation method

A clock circuit and clock signal technology, applied in the direction of electrical components, automatic power control, etc., can solve the problem of not being able to provide high-speed, wide-frequency clock signals, etc.

Pending Publication Date: 2020-02-28
XI AN UNIIC SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] The embodiment of the present application solves the technical problem that a high-speed, wide-frequency, and low-

Method used

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  • Clock circuit and clock signal generation method
  • Clock circuit and clock signal generation method
  • Clock circuit and clock signal generation method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0065] like figure 1 As shown, this embodiment provides a clock circuit, including:

[0066] The first inductance-capacitance phase-locked loop 1 (LC-PLL, Inductor Capacitor-PhaseLocked Loop) and the first ring-shaped phase-locked loop 2 (Ring-PLL, Ring-Phase Locked Loop) cascaded in sequence;

[0067] The first inductance-capacitance phase-locked loop 1 is used to perform frequency multiplication processing on the first input clock signal to generate a first high-frequency clock signal;

[0068] The first annular phase-locked loop 2 performs frequency multiplication processing on the first high-frequency clock signal based on a frequency configuration coefficient to generate a first target clock signal, and the frequency configuration coefficient is used to configure the first target clock signal Frequency of.

[0069]It should be noted that the first high-frequency clock signal provided by the first inductance-capacitance phase-locked loop 1 is a high-frequency clock signa...

Embodiment 2

[0099] like Figure 4 As shown, this embodiment provides a clock circuit, including:

[0100] A second inductance-capacitance phase-locked loop 3, a frequency divider 5 and a second annular phase-locked loop 4 cascaded in sequence;

[0101]The second inductance-capacitance phase-locked loop 3 is used to perform frequency multiplication processing on the second input clock signal to generate a second high-frequency clock signal;

[0102] The frequency divider 5 is used to perform frequency division processing on the second high-frequency clock signal to generate a third high-frequency clock signal;

[0103] The second annular phase-locked loop 4 performs frequency multiplication processing on the third high-frequency clock signal based on a frequency configuration coefficient to generate a second target clock signal, and the frequency configuration coefficient is used to configure the second target clock signal Frequency of.

[0104] As an optional embodiment, the frequency ...

Embodiment 3

[0144] like Figure 12 As shown, this embodiment provides a method for generating a clock signal, including:

[0145] Step S101: receiving the first input clock signal by the first inductance-capacitance phase-locked loop, and performing frequency multiplication processing on the first input clock signal to generate a first high-frequency clock signal;

[0146] Step S102: Perform frequency multiplication processing on the first high-frequency clock signal by the first annular phase-locked loop to generate a first target clock signal.

[0147] It should be noted that the first high-frequency clock signal generated by the first LC-type phase-locked loop is a high-frequency clock signal, and this high-frequency clock signal has the advantages of high frequency and low jitter (that is, good phase noise characteristics). The bandwidth of the first annular phase-locked loop is adjusted based on the frequency of the first high-frequency clock signal output by the first inductance-ca...

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PUM

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Abstract

The invention discloses a clock circuit. The clock circuit comprises a first inductance-capacitance type phase-locked loop and a first annular phase-locked loop, the first inductance-capacitance typephase-locked loop is used for carrying out frequency multiplication processing on a first input clock signal to generate a first high-frequency clock signal, and the first annular phase-locked loop isused for carrying out frequency multiplication processing on the first high-frequency clock signal to generate a first target clock signal. According to the present invention, the technical problem that a clock signal with high speed, wide frequency and low jitter cannot be provided in the prior art, is solved.

Description

technical field [0001] The invention relates to the technical field of clock generating circuits, in particular to a clock circuit and a clock signal generating method. Background technique [0002] Compared with the traditional DDR3 / 4 / LPDDR4 physical interface PHY, the graphic DRAM GDDR6 physical interface PHY needs to provide a data transmission rate up to 16Gbps, and the system level puts forward stricter requirements for the clock generation circuit. A High-speed, high-performance and low-jitter clock generation circuit, the specific requirements are as follows: [0003] 1. Need to provide a high-speed clock signal, the maximum speed can reach 8GHz. [0004] 2. It is necessary to provide a low-jitter clock signal so that the overall system is controlled within 0.2 unit time interval UI. [0005] 3. It is necessary to provide a clock signal that can cover a wide range of frequencies, and the supported frequency range is 5GH to 8GHz (especially 5 / 6 / 6.5 / 7 / 8GHz). [0006]...

Claims

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Application Information

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IPC IPC(8): H03L7/07H03L7/087H03L7/099H03L7/18
CPCH03L7/07H03L7/087H03L7/0992H03L7/18
Inventor 贾雪绒
Owner XI AN UNIIC SEMICON CO LTD
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