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Bit line screening method and device, storage equipment and storage medium

A screening method and bit line technology, applied in static memory, instruments, etc., can solve problems such as difficult detection

Active Publication Date: 2020-03-24
GIGADEVICE SEMICON (BEIJING) INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In the process of implementing the present invention, the inventor found that the prior art has the following defects: it is difficult to detect potential failed bit lines that will only appear after a period of use

Method used

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  • Bit line screening method and device, storage equipment and storage medium
  • Bit line screening method and device, storage equipment and storage medium
  • Bit line screening method and device, storage equipment and storage medium

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0043] figure 1 It is a flow chart of a bit line screening method provided by Embodiment 1 of the present invention. The method of this embodiment can be executed by a bit line screening device, which can be implemented by hardware and / or software, and can generally be integrated in the storage device. The method of this embodiment specifically includes:

[0044] S101. Apply the first detection voltage and the second detection voltage for a set time to all the bit lines in each of the independent detection areas at intervals by applying the same voltage, and at the same time respectively apply All the word lines are applied with cut-off voltage for a set time, wherein the voltage difference between the first detection voltage and the second detection voltage is greater than the set voltage difference.

[0045] In this embodiment, the area to be detected may specifically be a BLOCK area in NAND FLASH, or a BANK area in NORFLASH, and the like. The fact that the areas to be de...

Embodiment 2

[0059] figure 2 It is a flow chart of a bit line screening method provided in Embodiment 2 of the present invention. This embodiment is optimized on the basis of the above embodiments. In this embodiment, a specific source voltage application method is given. It is added to determine whether to discard the area to be detected according to the number of failed bit lines, and to increase the number of failed bit lines. Specific implementation of the replacement of the line and the replacement step of discarding the region to be detected.

[0060] Correspondingly, the method in this embodiment specifically includes:

[0061] S201. Apply the first detection voltage and the second detection voltage for a set time to all the bit lines in each of the independent detection areas at intervals, and respectively apply the same voltage to all the bit lines in each of the detection areas. All the word lines are applied with cut-off voltage for a set time, wherein the voltage difference ...

Embodiment 3

[0082] image 3 It is a structural diagram of a device for screening bit lines provided by Embodiment 3 of the present invention. Such as image 3 As shown, the device includes: a voltage application module 301, a programming module 302, a verification module 303 and a failure bit line determination module 304, wherein:

[0083] The voltage applying module 301 is used to respectively apply the first detection voltage and the second detection voltage for a set time to all the bit lines in each of the independent regions to be detected by applying the same voltage at intervals, and simultaneously apply each All word lines in the area to be tested apply cut-off voltages for a set time, wherein the voltage difference between the first detection voltage and the second detection voltage is greater than the set voltage difference;

[0084] A programming module 302, configured to perform a verification programming operation on each area to be tested, so that the data stored in any t...

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PUM

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Abstract

The embodiment of the invention discloses a bit line screening method and device, storage equipment and a storage medium. The method comprises the following steps: applying a first detection voltage and a second detection voltage with set time to all bit lines in each independent to-be-detected region in a manner of applying the same voltage at intervals, and applying a cut-off voltage with set time to all word lines in each to-be-detected region; performing inspection programming operation on each to-be-detected area to enable data stored in any two adjacent storage units in each to-be-detected area to be different; verifying whether the storage data of all the storage units in each to-be-detected area is matched with the verification programming operation or not; and determining the bitline corresponding to the storage unit of which the storage data is not matched with the check programming operation as a failure bit line. According to the technical scheme provided by the embodimentof the invention, the technical defect that potential failure bit lines are difficult to detect by the existing failure bit line detection method is overcome, and all failure bit lines can be rapidlyand accurately detected at one time.

Description

technical field [0001] The embodiments of the present invention relate to the technical field of storage device detection, and in particular, to a bit line screening method, device, storage device, and storage medium. Background technique [0002] For mass production of semiconductor devices, failure analysis of designed and manufactured semiconductor devices is an important means to increase yield and improve process technology reliability and stability. [0003] For semiconductor memory devices, a short circuit between bit lines is a common failure condition. A short circuit on a bit line will cause all memory cells on the two bit lines to lose their function, reducing the storage capacity of the memory chip. Therefore, for semiconductor Bit line failure analysis of memory devices is very important. In the prior art, it is specifically measured whether the voltage between every two bit lines exceeds the threshold through an electrical test (chip probing test), so as to fi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/50G11C29/00
CPCG11C29/50G11C29/006G11C29/838G11C2029/5004
Inventor 张赛苏如伟冯骏
Owner GIGADEVICE SEMICON (BEIJING) INC