Bit line screening method and device, storage equipment and storage medium
A screening method and bit line technology, applied in static memory, instruments, etc., can solve problems such as difficult detection
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Embodiment 1
[0043] figure 1 It is a flow chart of a bit line screening method provided by Embodiment 1 of the present invention. The method of this embodiment can be executed by a bit line screening device, which can be implemented by hardware and / or software, and can generally be integrated in the storage device. The method of this embodiment specifically includes:
[0044] S101. Apply the first detection voltage and the second detection voltage for a set time to all the bit lines in each of the independent detection areas at intervals by applying the same voltage, and at the same time respectively apply All the word lines are applied with cut-off voltage for a set time, wherein the voltage difference between the first detection voltage and the second detection voltage is greater than the set voltage difference.
[0045] In this embodiment, the area to be detected may specifically be a BLOCK area in NAND FLASH, or a BANK area in NORFLASH, and the like. The fact that the areas to be de...
Embodiment 2
[0059] figure 2 It is a flow chart of a bit line screening method provided in Embodiment 2 of the present invention. This embodiment is optimized on the basis of the above embodiments. In this embodiment, a specific source voltage application method is given. It is added to determine whether to discard the area to be detected according to the number of failed bit lines, and to increase the number of failed bit lines. Specific implementation of the replacement of the line and the replacement step of discarding the region to be detected.
[0060] Correspondingly, the method in this embodiment specifically includes:
[0061] S201. Apply the first detection voltage and the second detection voltage for a set time to all the bit lines in each of the independent detection areas at intervals, and respectively apply the same voltage to all the bit lines in each of the detection areas. All the word lines are applied with cut-off voltage for a set time, wherein the voltage difference ...
Embodiment 3
[0082] image 3 It is a structural diagram of a device for screening bit lines provided by Embodiment 3 of the present invention. Such as image 3 As shown, the device includes: a voltage application module 301, a programming module 302, a verification module 303 and a failure bit line determination module 304, wherein:
[0083] The voltage applying module 301 is used to respectively apply the first detection voltage and the second detection voltage for a set time to all the bit lines in each of the independent regions to be detected by applying the same voltage at intervals, and simultaneously apply each All word lines in the area to be tested apply cut-off voltages for a set time, wherein the voltage difference between the first detection voltage and the second detection voltage is greater than the set voltage difference;
[0084] A programming module 302, configured to perform a verification programming operation on each area to be tested, so that the data stored in any t...
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