Limited pin test interface with analog test bus overview

Abstract

Certain aspects of the disclosure are directed toward test control and test access configuration via two pins on an integrated circuit (IC). According to a specific example, an IC chip-based apparatusis used in connection with a controller for testing a target IC. The IC chip-based apparatus includes an event (capture) circuit configured and arranged to control logic states through which a statictest configuration is selected for a given event detected in response to a clock signal and to a data signal respectively derived from the controller. A test-operation control circuit may be configured and arranged to test the target IC by selectively configuring each of the clock pin and the I / O pin of the controller for use as an analog test bus, data input to the controller or data output fromthe controller, and carrying out dynamic operations by communicating test signals via pins of the target IC.

Description

technical field [0001] Aspects of various embodiments relate to test control and test access configuration through two pins on an integrated circuit (IC). Background technique [0002] The number of silicon dies tested in parallel on a single tester system continues to increase. However, devices that provide both digital and analog content have limited pins available for testing. Such devices may be present, for example, in in-vehicle networks, hearing devices, sensors, near field communication (NFC) devices and interface products, among others. In order to limit the cost of testing these silicon dies, a small number of pins may be contacted per die during testing. In some application areas (eg NFC, sensors), the die and / or even the package may only have a few pins for electrical access. These pins can be reused for production test access and / or in-system debug access. [0003] While some solutions exist for accessing on-chip features via a limited number of pins for pro...

AI Technical Summary

Problems solved by technology

As a result, it may not be possible to run tests natively on different tester systems, and the test speed provided by this solution is often limited, resulting in increased cost of testing silicon die

[0004] These and other issues have challenged the efficiency of test control and test access on ICs for a variety of applications

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