Preparation method of semiconductor structure

Abstract

The invention provides a preparation method of a semiconductor structure. The preparation method comprises the following steps: providing a to-be-etched layer; forming a core mold layer on the surfaceof the to-be-etched layer; forming a side wall material layer on the surfaces of the to-be-etched layer and the core mold layer; under the condition of applying continuous bias power and/or pulse bias power, etching back the side wall material layer by adopting a plasma etching process until the to-be-etched layer and the top of the core mold layer are exposed, and reserving the side wall materials on the two sides of the core mold layer as side walls; removing the core mold layer; and after the core mold layer is removed, etching the to-be-etched layer by taking the side walls as masks. By utilizing the method, the line width roughness of the semiconductor structure is sequentially controlled and reduced through different steps, and the pattern feature structure is accurately transferredto the substrate, so that the performance of the device is improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for preparing a semiconductor structure. Background technique [0002] With the evolution of semiconductor technology nodes and machines, chip manufacturers continue to challenge to increase the density of devices on the wafer under cost considerations. The density of devices in integrated circuits is getting higher and higher. The characteristic critical dimension (CD) of semiconductor devices ) is constantly decreasing, approaching the optical-physical limit of lithography, and the mask pattern formed by the existing lithography process is difficult to meet the demand for the continuous reduction of the critical dimension of semiconductor devices, which curbs the development of semiconductor technology. [0003] In order to further reduce the size of semiconductor devices on the basis of the existing photolithography process, the self-aligned double patternin...

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Problems solved by technology

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a method for preparing a semiconductor structure, which is used to solve the problem that the line width roughness is too high when the self-aligned double patterning (SADP) process is adopted in the prior art, This leads to local bridging of subsequent devices, which in turn causes deformation of the threshold voltage distribution and affects the performance of the device.

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