Embedded processor of storage and calculation integrated chip, instruction set and data processing method

Abstract

The invention discloses an embedded processor of a storage and calculation integrated chip, an instruction set and a data processing method. The method comprises the following steps that: 1) an embedded processor directly reads data from an input data cache through a data input interface; 2) when a storage and calculation integrated array performs artificial neural network calculation, the storageand calculation integrated array sends data to be processed into storage and calculation integrated array/logic, controls a DAC to convert the data into analog signals and then perform matrix multiplication and addition operation, and then controls an ADC to convert operation results into digital signals; 3) the embedded processor reads back the operation results and performs operation or activation operation on the operation results, caches intermediate data, and then judges whether current operation is the last layer of neural network operation or not; (4) if the current operation is not the last layer of neural network operation, the step (2) and the step (3) are carried out circularly, and if the current operation is the last layer of neural network operation, the step (5) is carriedout; and (5) the embedded processor carries out final result processing, judges an artificial neural network recognition result and determines whether to output a result or not according to the recognition result.

Description

technical field [0001] The invention relates to an integrated storage and calculation chip, in particular to an embedded processor, an instruction set and a data processing method of the integrated storage and calculation chip. Background technique [0002] With traditional von Neumann computing architectures, the processor and memory are separate. When this computing architecture is applied to artificial neural network operations, a large amount of data access and computing operations are required, and the computing power consumption is high, the time is long, and the efficiency is low, which can no longer meet the applications of most scenarios, especially low power consumption. , low-latency edge computing application scenarios. [0003] In order to break through this bottleneck, the chip based on the integrated computing architecture of storage and calculation has been developed rapidly. The basic idea is to directly use the storage unit to perform multiplication and ad...

AI Technical Summary

Problems solved by technology

In the storage-computing integrated chip, the control efficiency of the general-purpose embedded central processing unit (CPU) or microcontroller (MCU) designed for the characteristics of the storage-computing integrated chip is low, and some calculations related to artificial neural networks (such as various Activation function conversion, pooling operations in convolutional neural networks, etc.) require additional circuit logic to achieve, and there is no control logic circuit that matches the core computing array / logic of the integrated storage and calculation, which is not conducive to the rapid development of integrated storage and calculation chips and integration

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