Network-on-chip topological structure and implementation method thereof

Abstract

The invention discloses a network-on-chip topological structure and an implementation method thereof, the topological structure comprises a plurality of transmission layer routing nodes of a Tile structure, and parameters such as the number of ports, the number of virtual channels and the depth of port FIFO of the transmission layer routing nodes can be flexibly configured; through architecture design and layout planning based on Tile, the problems that hardware resources are greatly expanded, and physical design and rear-end implementation are difficult due to the fact that the number of switching matrixes of an on-chip network of an existing multi-core on-chip system is large and the scale is too large can be solved; according to the implementation method of the topological structure, through system modeling and performance optimization, optimized on-chip network transmission layer parameters can be obtained, key components of an on-chip network are directly converted into hardware circuits through a hardware generator, and it is ensured that the on-chip network PPA is optimized; according to the scheme, the delay of a message routing assembly line and a key path can be optimized, and the on-chip network can be ensured to work normally under a relatively high main frequency.

Description

technical field [0001] Embodiments of the present invention relate to the field of network-on-chip technology of a multi-core system-on-chip, and specifically relate to a network-on-chip topology and an implementation method thereof. Background technique [0002] With the maturity of integrated circuit technology, the number of IP cores integrated in a single chip is increasing, and the traditional shared bus interconnection structure has been unable to meet the growing demand for on-chip communication. Network-on-Chip (NoC) technology It is more and more widely used in multi-core system-on-chip, and its core idea is to borrow computer network technology to effectively solve the limitations of the traditional shared bus interconnection structure. The network on chip mainly includes a network interface (Network Interface, NI), one or more routing nodes (Router) and data links (Channel). The data generated by the IP core is packaged through the network interface and sent to th...

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Problems solved by technology

[0005] To this end, the embodiments of the present invention provide a network-on-chip topology and its implementation method to solve the problem of greatly expanding hardware resources and physical design problems caused by the large number of switching matrices and the large scale of the network-on-chip of the existing multi-core system-on-chip. and back-end implementation difficulties

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