CMOS image sensor structure and manufacturing method

Abstract

The invention discloses a CMOS image sensor structure. The structure is arranged on a first silicon substrate and a second silicon substrate which are stacked up and down, the first silicon substratecomprises a first buried oxide layer and a first silicon layer arranged below the first buried oxide layer, the second silicon substrate comprises a second buried oxide layer and a second silicon layer arranged below the second buried oxide layer, the thickness of the first silicon layer is greater than that of the second silicon layer, the first silicon layer is bonded with the second buried oxide layer, a through opening is formed on the second silicon substrate corresponding to the pixel unit array area, a plurality of photosensitive parts and control transistors of the pixel unit array arearranged on the back surface of the first silicon layer corresponding to the position of the opening, and peripheral circuit transistors are arranged on the back surface of the second silicon layer around the opening. According to the invention, the manufacturing of the pixel unit of the backside illuminated image sensor can be realized while a low-power SOI device is used in a peripheral circuit, and the problems of impurity self-doping and poor thickness uniformity after thinning easily caused by a conventional backside illuminated process can be avoided.

Description

technical field [0001] The invention relates to the technical field of semiconductor processing, in particular to a CMOS image sensor structure and a manufacturing method. Background technique [0002] For half a century, the semiconductor industry has been shrinking transistor size, increasing transistor density, and improving performance in accordance with Moore's Law. However, as the size of bulk silicon transistor devices with planar structure is getting closer and closer to the physical limit, Moore's law is getting closer and closer to its end; therefore, some new structures of semiconductor devices called "non-classical CMOS" have been proposed . These technologies include FinFET, carbon nanotubes, silicon on insulator (silicon on insulator, SOI), silicon germanium on insulator (SiGe on insulator, SiGeOI) and germanium on insulator (Ge on insulator, GeOI), etc. [0003] Through these new structures, the performance of semiconductor devices can be further improved. ...

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Problems solved by technology

Since the doping concentrations of the highly doped substrate 15 and the device silicon layer 14 are different, their corresponding etching rates are also different, so the etching process is mainly stopped by the different etching rates between the two, but the difference in doping concentration The resulting difference in corrosion rate is small, so the end point of corrosion stop is not easy to control, often causing over-corrosion phenomenon; at the same time, the impurity concentration in the highly doped substrate 15 is relatively high, and it is easy to precipitate during the high temperature process, thereby affecting device characteristics

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