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Packaging method

A packaging method and a technology of plastic packaging layer, which are applied in the direction of semiconductor devices, electrical components, circuits, etc., can solve the problems that the performance of the packaging structure needs to be improved, and achieve the effect of improving the packaging effect, performance, electrical performance and reliability

Active Publication Date: 2022-07-08
NINGBO SEMICON INT CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The performance of the packaging structure formed by the packaging method of the prior art still needs to be improved

Method used

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Experimental program
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Embodiment Construction

[0015] It can be known from the background art that the performance of the package structure manufactured by using the existing package method needs to be improved.

[0016] Now combined with a packaging method to analyze, the packaging method is fan-out wafer-level packaging fake and inferior, Figure 1 to Figure 4 It is a schematic cross-sectional structure diagram of a fan-out wafer-level packaging process, and the packaging method includes the following steps:

[0017] refer to figure 1 , a substrate 10 is provided, the substrate 10 has a plurality of chips 20, and the chips 20 have an electrical connection structure 30 inside, the surface of the chip 20 exposes the surface of the electrical connection structure 30, and the surface of the electrical connection structure 30 is exposed between the adjacent chips 20. A plastic encapsulation layer 40 is formed on the substrate 10 ; a redistribution-layer (RDL, Redistribution-Layer) 50 is formed on the surface of each chip 20 ...

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PUM

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Abstract

The invention provides a packaging method, comprising: providing a plurality of chips, an electrical connection structure is formed in the chip, the surface of the electrical connection structure is exposed on the front side of the chip, a plastic sealing layer is formed between adjacent chips, and the front side of the chip is connected to the surface of the electrical connection structure. The surface of the plastic encapsulation layer has a plurality of solder ball regions and passivation regions between adjacent solder ball regions; a redistribution layer electrically connected to the electrical connection structure is formed on the front side of each chip, and each redistribution layer spans the solder balls a ball area and a passivation area adjacent to the solder ball area; forming solder balls electrically connected to the redistribution layer on the redistribution layer of the solder ball area; The rewiring layer, the front side of the chip and the surface of the plastic encapsulation layer in the passivation area are sprayed with slurry, and the slurry in the passivation area is cured to form a passivation layer in the passivation area. The present invention utilizes selective spraying to form the passivation layer, reduces the damage introduced by the passivation layer forming process, and further improves the reliability of the formed packaging structure.

Description

technical field [0001] The present invention relates to the technical field of semiconductor packaging, in particular to a packaging method. Background technique [0002] With the development trend of VLSI, the feature size of integrated circuits continues to decrease, and people's requirements for the packaging technology of integrated circuits continue to increase accordingly. Existing packaging technologies include Ball Grid Array (BGA), Chip Scale Package (CSP), Wafer Level Package (WLP), 3D Packaging (3D) and System in Package (Systemin Package). , SiP) etc. [0003] The formation of solder balls is one of the key technologies in the packaging process. The solder balls are electrically connected to the electrical connection structure in the chip, and the positions and numbers of input / output pins of the package structure are rearranged by using the solder balls, so as to facilitate the electrical connection between the package structure and external circuits or other ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/60H01L21/56
CPCH01L24/03H01L24/97H01L21/561H01L2224/0231H01L2224/97
Inventor 秦晓珊
Owner NINGBO SEMICON INT CORP