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Preparation method of standard sub-cell of four-junction gallium arsenide solar cell

A standard sub-cell and solar cell technology, applied in the field of standard sub-cell preparation of four-junction gallium arsenide solar cells, can solve the problems of complex process, high cost, difference in spectral response, etc., and achieve simplified process steps, good consistency, cost saving effect

Active Publication Date: 2020-07-17
CHINA ELECTRONIC TECH GRP CORP NO 18 RES INST
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

On the one hand, this method requires four epitaxy processes, which is complex and costly. On the other hand, there is always a difference between the sub-cell structure grown separately and the sub-cell structure grown as a whole of the four-junction cell, resulting in a difference in spectral response between the two.

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  • Preparation method of standard sub-cell of four-junction gallium arsenide solar cell
  • Preparation method of standard sub-cell of four-junction gallium arsenide solar cell
  • Preparation method of standard sub-cell of four-junction gallium arsenide solar cell

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Embodiment Construction

[0032] In order to further understand the invention content, characteristics and effects of the present invention, the following examples are given, and detailed descriptions are as follows in conjunction with the accompanying drawings:

[0033] Such as Figure 1 to Figure 5 Shown, technical scheme of the present invention is:

[0034] A standard sub-cell preparation method for a four-junction gallium arsenide solar cell, comprising:

[0035] Please check figure 1 1. Using metal-organic chemical vapor deposition (MOCVD) to forward grow four-junction gallium arsenide solar cells, and sequentially grow Ge (0.67eV) cells 102, InGaAs (1.1eV) cells 103, AlGaAs (1.5eV) cells on a germanium substrate 101 ) battery 104, AlGaInP (1.95eV) battery 105.

[0036] Please check figure 2 1. Prepare a Ge (0.67eV) standard sub-cell based on a four-junction gallium arsenide solar cell as a whole. On the front of the four-junction cell epitaxial wafer, the upper electrode grid line pattern ...

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Abstract

The invention discloses a preparation method of a standard sub-cell of a four-junction gallium arsenide solar cell, and belongs to the technical field of solar cells. The method is characterized by comprising the following steps: S1, positively growing the four-junction gallium arsenide solar cell by adopting a metal organic chemical vapor deposition technology, and sequentially growing a 0.67 eVGe cell, a 1.1 eV InGaAs cell, a 1.5 eV AlGaAs cell and a 1.95 eV AlGaInP cell on a germanium substrate; S2, preparing a 0.67 eV Ge standard sub-cell on the basis of the whole four-junction gallium arsenide solar cell; S3, preparing a 1.1 eVInGaAs standard sub-cell on the basis of the whole four-junction gallium arsenide solar cell; S4, preparing a 1.5 eV AlGaAs standard sub-cell on the basis of the whole four-junction gallium arsenide solar cell; and S5, preparing a 1.95 eVAlGaInP standard sub-cell on the basis of the whole four-junction gallium arsenide solar cell.

Description

technical field [0001] The invention belongs to the technical field of solar cells, and in particular relates to a preparation method of a standard sub-cell of a four-junction gallium arsenide solar cell. Background technique [0002] In the design stage of the solar cell array of the aerospace vehicle, the design parameters are mainly based on the test data of the solar cells. The solar cell array is usually composed of a large number of solar cell cells, and the slight error in the test results of the electrical performance of the solar cell cells will affect the solar cells. The design and development of battery arrays have a serious impact. If the test result is too high, the actual output power of the solar cell array will not meet the design requirements, resulting in insufficient power supply; if the test result is too low, it will lead to an increase in the area, weight and cost of the solar cell array, resulting in a waste of resources. Accurately testing the elect...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L31/0304H01L31/0725H01L31/0735H01L31/18
CPCH01L31/0304H01L31/0725H01L31/0735H01L31/1844Y02P70/50
Inventor 薛超孙强刘如斌张启明张恒
Owner CHINA ELECTRONIC TECH GRP CORP NO 18 RES INST
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