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Memory and method of forming the same

A memory and node technology, applied in semiconductor devices, electrical solid state devices, semiconductor/solid state device manufacturing, etc., can solve the problems of increasing difficulty and complexity of the memory manufacturing process, reducing manufacturing efficiency, etc., to reduce parasitic capacitance and simplify manufacturing Process, the effect of improving efficiency

Active Publication Date: 2022-03-29
FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Each insulating pattern 400' here includes two film layers (stacked insulating material layer 410' and mask material layer 420'), and the functions of the two film layers in subsequent steps are actually the same, so The use of two film layers to form the insulating pattern 400' increases the difficulty and complexity of the memory manufacturing process and reduces the manufacturing efficiency.

Method used

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  • Memory and method of forming the same
  • Memory and method of forming the same
  • Memory and method of forming the same

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Experimental program
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Embodiment 2

[0114] Such as Figure 5a or 5b, the difference from Embodiment 1 is that in this embodiment, the metal oxide layer 600b fills a part of the depth of the recess, so that there is a gap between the metal oxide layer 600b and the insulating pattern 400a An air gap G2 is formed between them. That is, the bottom of the metal oxide layer 600b extends from the top of the insulating pattern 400a into the first opening, so that the bottom of the metal oxide layer 600b is lower than the top of the insulating pattern 400a.

[0115] Specifically, see Figure 5a , when the first oxide layer 500a is formed, the first oxide layer 500a not only covers the insulating pattern 400a, but also completely fills a partial depth of the recess. see Figure 5b , when the metal oxide layer 600b is formed to cover the part of the insulating pattern 400a, the metal oxide layer 600b not only covers the insulating pattern 400a, but also fills a part of the depth of the depression. In this way, the uppe...

Embodiment 3

[0120] Such as Figure 6a or 6b, different from the first and second embodiments, in this embodiment, the metal oxide layer 600b completely fills the recess, so that the metal oxide layer 600b is insulated from the No air gap is formed between the patterns 400a.

[0121] Specifically, see Figure 6a , when the first oxide layer 500a is formed, the first oxide layer 500a not only covers the insulating pattern 400a, but also completely fills the recess. see Figure 6b , when the metal oxide layer 600b is formed to cover the portion of the insulating pattern 400a, the metal oxide layer 600b not only covers the insulating pattern 400a, but also completely fills the recess. In this way, the recesses are all filled with the medium, so that there is no air gap.

[0122] The method for forming the memory in this embodiment may be the same as the method for forming the memory in Embodiment 1, the only difference is that when forming the first oxide layer 500a and the metal oxide la...

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Abstract

The present invention provides a memory and its forming method. The insulating pattern covers at least the sidewall of the first opening of the spaced node contact structure and extends upward to be higher than the node contact structure. The upper surface of the insulating pattern is also toward the first opening. The center is depressed to form a depression, so that the insulating pattern formed by the existing two film layers can be replaced by one film layer, thereby omitting the grinding removal of a part of the thickness of the insulating material layer and the re-formation of the mask material layer in the prior art steps, which simplifies the preparation process of the memory and improves the preparation efficiency, and since the surface of the substrate is usually flattened by multiple grinding processes when forming the capacitor structure, even if the surface of the insulating pattern is uneven, it will not affect the memory performance is affected.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a memory and a forming method thereof. Background technique [0002] A memory, such as a dynamic random access memory (DRAM), generally has a memory cell array, and the memory cell array includes a plurality of memory cells arranged in an array. The memory has a plurality of word line structures and bit line structures, the word line structures are buried in the substrate, the bit line structures are formed on the substrate and electrically connected with corresponding memory cells, and the memory also includes a capacitor structure , the capacitance structure is used to store charges representing stored information, and the storage units can be electrically connected to the capacitance structure through a node contact structure, so as to realize the storage function of each storage unit. [0003] Figure 1a ~ Figure 1e It is a schematic structural diagram fo...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/108H01L21/8242H10B12/00
CPCH10B12/315H10B12/03H10B12/30
Inventor 颜逸飞冯立伟陈凯评
Owner FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD