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Semiconductor device and manufacturing method thereof, integrated circuit and electronic equipment

A manufacturing method and semiconductor technology, which are applied in the manufacture of semiconductor/solid-state devices, semiconductor devices, circuits, etc., can solve the problems of leakage of the channel layer, difficulty in electrode extraction, and degradation of the working performance of vertical nanowire ring gate devices, so as to improve the gate control ability, suppressing channel leakage, and improving performance

Active Publication Date: 2020-07-28
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] However, the traditional vertical nanowire gate-all-around device makes it difficult to extract electrodes due to its own structural problems.
Although some vertical nanowire gate-around devices with new structures can solve the problem of electrode lead-out difficulties, the channel layer on them is prone to leakage, which leads to the degradation of the working performance of vertical nanowire gate-around devices.

Method used

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  • Semiconductor device and manufacturing method thereof, integrated circuit and electronic equipment
  • Semiconductor device and manufacturing method thereof, integrated circuit and electronic equipment
  • Semiconductor device and manufacturing method thereof, integrated circuit and electronic equipment

Examples

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Embodiment 1

[0055] An embodiment of the present invention provides a semiconductor device, such as Figure 33 to Figure 36 As shown, the semiconductor device includes a substrate 1, a stack structure 2 and a gate stack structure 6; wherein, the substrate 1 may be a silicon substrate, a germanium substrate, or a silicon-on-insulator substrate, etc., which will not be listed here.

[0056] The above stacked structure 2 is formed on the surface of the substrate 1 . The stack structure 2 includes a first electrode layer 3 , a channel layer 4 and a second electrode layer 5 . The first electrode layer 3 , the channel layer 4 and the second electrode layer 5 are stacked on the substrate 1 along a direction away from the substrate 1 . The channel layer 4 includes a channel support portion 8 and a channel material portion 9, the channel material portion 9 is formed on the periphery of the channel support portion 8, the bottom end of the channel support portion 8 is in contact with the top end of ...

Embodiment 2

[0078] An embodiment of the present invention provides a method for manufacturing a semiconductor device, such as Figure 37 As shown, the manufacturing method of the semiconductor device includes:

[0079] Step S101, such as figure 2 As shown, a substrate 1 is provided. As for the selection of the substrate 1, reference may be made to the foregoing, and details are not repeated here.

[0080] Step S102, such as Figure 3 to Figure 26As shown, a stacked structure 2 is formed on the surface of the substrate 1, the stacked structure 2 includes a first electrode layer 3, a channel layer 4 and a second electrode layer 5, the first electrode layer 3, the channel layer 4 and the second electrode layer 5 is distributed along the thickness direction of the substrate 1, the channel layer 4 includes a channel support portion 8 and a channel material portion 9, the channel material portion 9 is formed on the outer periphery of the channel support portion 8, and the bottom of the chan...

Embodiment 3

[0117] An embodiment of the present invention provides an integrated circuit, and the integrated circuit includes the semiconductor device described in the first embodiment above. It should be understood that the semiconductor device may be manufactured by using an existing process or the manufacturing method described in the second embodiment above.

[0118] The beneficial effect of the integrated circuit provided by the embodiment of the present invention is the same as that of the semiconductor device provided by the first embodiment above, and will not be repeated here.

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Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, an integrated circuit and electronic equipment, relates to the technical field of semiconductors, and aims to suppress a channel electric leakage phenomenon and improve the performance of the semiconductor device. The semiconductor device includes a substrate, a stacked structure, and a gate stack structure, whereinthe stacked structure is formed on the surface of the substrate; the stacked structure includes a first electrode layer, a channel layer, and a second electrode layer which are stacked on the substrate in a direction away from the substrate; the channel layer includes a channel supporting part and a channel material part; the channel material part is formed on the periphery of the channel supporting part; the bottom end of the channel supporting part is in contact with the top end of the first electrode layer; the top end of the channel supporting part is in contact with the second electrodelayer; the channel material part is in contact with the first electrode layer and the second electrode layer; the channel supporting part is a non-conductive part; and the gate stack structure surrounds the periphery of the channel material part. The manufacturing method of the semiconductor device is used for manufacturing the semiconductor device. The semiconductor device provided by the invention is applied to the electronic equipment.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof, an integrated circuit and electronic equipment. Background technique [0002] The vertical nanowire gate-around device is a new complementary metal oxide semiconductor transistor, which can increase the operating current and reduce the short channel effect. Therefore, the vertical nanowire gate-around device has good gate control ability and broad application prospects. [0003] However, the traditional vertical nanowire gate-all-around device makes it difficult to extract electrodes due to its own structural problems. Although some vertical nanowire gate-around devices with new structures can solve the problem of electrode lead-out difficulties, the channel layer on them is prone to leakage, which leads to the degradation of the working performance of the vertical nanowire gate-around devices. Contents of the inven...

Claims

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Application Information

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IPC IPC(8): H01L29/78H01L29/06H01L29/10H01L21/336
CPCH01L29/7828H01L29/0607H01L29/0669H01L29/0684H01L29/1033H01L29/66666
Inventor 顾杰吴振华张亚东殷华湘
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI