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Gate manufacturing method

A manufacturing method and gate technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of germanium silicon layer 250 damage, uneven thickness, affecting the performance of semiconductor devices, etc., to achieve protection from damage, The effect of improving device performance

Active Publication Date: 2020-07-31
SHANGHAI HUALI INTEGRATED CIRCUTE MFG CO LTD
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Problems solved by technology

And in one embodiment, after the formation of the first nitride layer 310, the surface treatment of the first nitride layer 310 will be performed with O2 or O3, so that an oxide layer will be formed on the surface of the first nitride layer 310, This process will consume a certain thickness of the first nitride layer 310, and the first nitride layer 310 may have a problem of uneven thickness due to the formation process. If the first nitride layer in some areas is very thin, then use O2 Or O3 during the surface treatment of the first nitride layer 310 to form an oxide layer or in the subsequent photoresist back etching process, there is a risk of etching through the first nitride layer 310, resulting in the silicon germanium layer 250 damage, which affects the performance of semiconductor devices

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Embodiment Construction

[0020] The technical solutions in the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0021] In an embodiment of the present invention, it is to provide a method for fabricating a gate to improve the performance of a semiconductor device (especially a p-type field effect transistor). The method for fabricating a gate in an embodiment of the present invention includes: S1: providing a semiconductor substrate, forming a field oxide layer in the semiconductor substrate, isolating an active region by the field oxide layer, and forming a P well in the active region region and N-well region; S2: sequenti...

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Abstract

The invention relates to a gate manufacturing method, and to semiconductor manufacturing technology, the method comprises the steps of after dummy gate formation, forming a first nitride layer, the first nitride layer covers the top of the dummy gate, the top and side surfaces of the side walls at two sides of the dummy gate, and an area between the dummy gates; then forming a first oxide layer covering the surface of the first nitride layer through a deposition process, so that the first nitride layer is prevented from being etched through in a subsequent process, the germanium-silicon layeris further protected from being damaged, and the performance of the device is improved.

Description

technical field [0001] The invention relates to semiconductor manufacturing technology, in particular to a gate manufacturing method. Background technique [0002] The HKMG process such as 28nm HKMG is a common process for manufacturing semiconductor devices, which requires the formation of a high dielectric constant (HK) gate dielectric layer and the formation of a metal gate (MG) at the same time. [0003] Specifically, see figure 1 , figure 1 It is a schematic diagram of one of the semiconductor device manufacturing processes of an embodiment. Such as figure 1 As shown, in the existing HKMG process, the metal gate last process is usually adopted. In the metal gate last process, the polysilicon gate 211 is usually used as the dummy gate structure to form the gate dielectric layer, channel region, and source of the device. In the drain region, the metal gate is then replaced, that is, the polysilicon gate 211 is removed, and the area where the polysilicon gate 211 is re...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8238
CPCH01L21/8238H01L21/823864H01L21/823814
Inventor 周思敏陈守钧
Owner SHANGHAI HUALI INTEGRATED CIRCUTE MFG CO LTD