A Virtual Multi-Channel SDRAM Access Method Supporting Flexible Block Access

Abstract

The invention belongs to the field of storage technology, and discloses a virtual multi-channel SDRAM access method that supports flexible block access, uses FIFO to isolate different clock domains, and performs cross-clock domain processing, data splicing, and data caching, so it supports different channels in different channels. Read and write data in the clock domain; perform sequential write address calculations, sequential read address calculations, and block read address calculations during sequential access and block access to SDRAM; schedule switching between multiple channels, and perform multi-channel switching Arbitrate and control the amount of data read and written each time; the SDRAM controller connects the user layer interface and SDRAM; and converts the read and write addresses, commands, and data into correct timing relationships and sends them to the SDRAM bus. The invention can reduce the logic resource occupation of FPGA, rationally utilize the limited bus bandwidth of SDRAM, improve the utilization rate of SDRAM bus bandwidth and improve the bandwidth capability.

Description

technical field [0001] The invention belongs to the technical field of storage, and in particular relates to a virtual multi-channel SDRAM access method supporting flexible block access. Background technique [0002] At present, with the rapid development of the aerospace industry and the continuous development and updating of satellites such as the Beidou series, the relay satellite network can already cover areas around the world, but there is no ability to establish ground receiving stations around the world, so the satellites sent are very difficult It is difficult to receive all the data through the ground receiving station, and it needs to rely on the relay network for relay transmission. The bandwidth of the relay network is limited. In order to realize the transmission of a large amount of data under the limited bandwidth, a large number of large Capacity storage is used to complete the collection, storage, and real-time processing of on-board data, and they play an ...

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Problems solved by technology

[0011] The difficulty of solving the above problems and defects is as follows: 1. When calculating the block address, the address calculation method will also change with the different image format and block size, so the calculation is more complicated, and the corresponding logical resource consumption is also relatively large. How to design a simple and effective address block method is a big difficulty;

[0012] 2. The difficulty in the design of multi-condition arbitration lies in the judgment of the arbitration conditions. Different channels have great differences in bit width, bandwidth, frequency, and data importance. It is extremely important to select appropriate conditions for channel priority arbitration and switching. Affected the effect of arbitration

[0013] 3. The difficulty in the refresh of the controller is mainly reflected in the conflict between the refresh operation and the burst read and write operations. On the one hand, the storage structure of the SDRAM requires that the storage unit be refreshed at intervals to maintain data, and on the other hand On the one hand, because reading and writing are all burst operations, other operations cannot be performed during burst operations. When a burst operation is in progress and a refresh request is received, this conflict will be triggered:

[0014] If it is not refreshed, data loss may occur, but if it is refreshed, the current burst process will be interrupted and the current read and write operations will be affected. Therefore, how to coordinate this contradiction is a major difficulty

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