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4M 1553 bus transceiver system-level test system and test method

A bus transceiver and test system technology, applied in the transmission system, digital transmission system, electronic circuit test, etc., can solve the problems of difficult application environment verification, cost a lot of working time, transceiver system-level testing problems, etc. Achieve the effect of reducing development cost and cycle, fast measurement speed and good integration

Active Publication Date: 2020-08-11
XIAN MICROELECTRONICS TECH INST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The maximum number of nodes in the 4M 1553 bus communication network is 32. Since the main line of the entire communication network is long and there are many branch lines, in the actual network construction process, the parasitic impedance introduced by different application environments has certain differences. This complex application environment It brings a lot of trouble to the system-level test of the transceiver. It takes a lot of work time to build a communication network verification system with the maximum number of nodes when testing and verifying each batch of circuit systems. Even if the network communication system with the maximum number of nodes is built, It is also difficult to simulate complex application environments to verify comprehensive

Method used

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  • 4M 1553 bus transceiver system-level test system and test method
  • 4M 1553 bus transceiver system-level test system and test method

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Experimental program
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Embodiment

[0038] Such as figure 1 As shown, the 4M 1553 bus transceiver system parameter test is carried out based on the above test method. Among them, the transceiver to be tested adopts LRT2004 type 4M 1553 bus transceiver, and the transformer unit adopts LS3067-3 transformer; The second transceiver to be tested is connected to the 3.3V DC power supply; after the power is stable, the field programmable gate array FPGA unit work indicator light is on, and the field programmable gate array FPGA unit generates a 4M 1553 bus Manchester code signal and transmits it to the first transceiver to be tested. The first transceiver to be tested drives its equivalent resistance, and the first input terminal A and the second input terminal B of the oscilloscope resistance network unit are used to test the output signal amplitude, rising edge, falling edge, delay and Zero-crossing interval system parameters, test waveforms such as figure 2 As shown, the test data is shown in Table 1; the pulse ...

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Abstract

The invention discloses a 4M 1553 bus transceiver system-level test system and a 4M 1553 bus transceiver system-level test method. The 4M 1553 bus transceiver system-level test system is composed of aresistor network unit, a first transformer unit and a second transformer unit. The resistance network unit is used for adjusting the output amplitude of the output signal end of the transceiver. Thetransformer unit is combined to realize stable transmission of signals; tests of transceivers in all application environments of 4M 1553 bus communication can be covered; the 4M 1553 bus transceiver test system is simple in circuit structure, good in integration level and accurate in test result, compared with a test method for building a communication network, the development cost and period of the test system can be reduced to a great extent, test verification is comprehensive and reliable, and test reliability guarantee is provided for application and development of the 4M 1553 bus transceiver.

Description

technical field [0001] The invention relates to the technical field of integrated circuit testing, in particular to a 4M 1553 bus transceiver system-level testing system and testing method. Background technique [0002] The schematic diagram of the 4M 1553 bus transceiver circuit is as follows image 3 As shown, according to the system requirements, the sending module drives and outputs two out-of-phase signals through external logic input, and the rising and falling times of the signals have certain requirements, and then is coupled to the system bus through a transformer, that is, the single-level Manchester code is converted into Bi-level Manchester code; the input of the receiving module is the signal of the bus signal coupled by the transformer, and the output is two inverting logic signals, which control the logic part of the 4M 1553 bus controller, that is, convert the bi-level Manchester code into a single-level Manchester Yard. The maximum number of nodes in the 4M...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28
CPCG01R31/2851H04L2012/40208Y02P90/02
Inventor 季轻舟王勇吴龙胜
Owner XIAN MICROELECTRONICS TECH INST
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