Quick verification system for operation result
A computing result and fast technology, applied in the field of data computing, can solve the problem of high hardware resource consumption, etc., and achieve the effect of small resource consumption, satisfying real-time performance, and saving resource consumption
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Embodiment 1
[0026] Such as figure 1 As shown, the present embodiment provides a quick check system for calculation results, the system is suitable for DSP chips, the DSP chip includes a calculation unit, the calculation unit is used to perform target calculation conversion according to input data to obtain corresponding output data, input Both the data and the output data are arrays, and the target operation may include: DCT operation, (I)DCT operation, DFT operation, (I)DFT operation, etc.
[0027] Specifically, in this embodiment, the transformation matrix W of the input data is set to satisfy the following formula:
[0028] W·W T =kE
[0029] In the formula, E is the identity matrix, and k is a constant.
[0030] For the convenience of description, it is assumed that the input data in this embodiment is an array composed of real numbers, and the operation unit performs DCT operation, and at this time, the operation unit performs serial input calculation.
[0031] On the basis of th...
Embodiment 2
[0044] For the arithmetic units that perform parallel multi-way operations, it is necessary to set the same number of first check units and second check units according to the number of parallel branches, and set the corresponding adders, and use the adders to check the check units. The calculated data is added to complete the verification of the correctness of the output data. In this embodiment, the parallel two-way operation is taken as an example, and the description is made on the basis of the first embodiment above.
[0045] Such as figure 2 As shown, the second embodiment provides a quick verification system for calculation results. When the calculation unit executes two parallel input data calculations, the system is provided with two first verification units and two second verification units in parallel. unit, the system also includes: a first adder and a second adder;
[0046] A first checking unit is respectively set at the two input terminals of the arithmetic u...
Embodiment 3
[0050] Such as image 3 As shown, on the basis of the first and second embodiments above, the third embodiment provides a quick verification system for the calculation results. When the calculation unit performs DFT and IDFT operations, the input data includes two parts, the real part and the imaginary part. At this time, the square unit in the first (second) checking unit in this embodiment includes: a first multiplier, a second multiplier and a third adder; the first multiplier is used to calculate the input data of the square unit The square of the real part; the second multiplier is used to calculate the square of the imaginary part of the input data of the square unit; the third adder is used to calculate the sum of the square of the real part and the square of the imaginary part, and record the sum as the square unit output, and then output the sum value to the accumulation unit to complete the operation of the first (second) check unit.
[0051] Specifically, when perf...
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