Fabrication method of semiconductor structure
A semiconductor and channel technology, which is applied in the field of semiconductor structure preparation, can solve the problems of channel hole penetration and roundness, and achieve the effects of improving penetration and roundness, reducing by-products, and reducing feature size
Active Publication Date: 2021-11-12
YANGTZE MEMORY TECH CO LTD
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Problems solved by technology
[0004] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a method for preparing a semiconductor structure, which is used to solve the problem that some channel holes in the prior art are easily affected by the surrounding structural environment, so that the channel in this region The penetration and roundness of the channel holes are greatly affected, etc.
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[0064]Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.
[0065] For example, when describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, which should not limit the protection scope of the present invention. In addition, the three-dimensional space dimensions of length, width and depth shou...
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Abstract
The present invention provides a preparation method of semiconductor structure. The preparation methods include: providing semiconductor bases, including adjacent channel pores and grille barriers; formation of etching mask layer, including several in the channel -hole areaThis dounton graphic and virtual shallow grooves corresponding to the gate partition area; carved semiconductor bases to form a channel hole in the channel hole area.The present invention forms a virtual shallow groove on the corpus cover layer corresponding to the grille partition area, which can reduce the etching mask material at the location, and reduce the by -products generated by the etching membrane material.During the erosion process, the impact of the above -mentioned by -products on the eclipse of the channel can be reduced.The structural environment of the inner pores and outer pores of the channel hole can improve the penetration and circularity of the channel hole, which is conducive to improving the consistency of the inner and outer pores.
Description
technical field [0001] The invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a method for preparing a semiconductor structure. Background technique [0002] At present, the memory cells of the three-dimensional memory are all formed in the channel holes with high aspect ratio, and the channel holes with high aspect ratio are usually realized by plasma dry etching. The degree and penetration directly determine the storage performance of the device. The current channel holes are arranged in various ways. During the formation process, some channel holes, such as the outer row of holes in the 9 rows of holes, are easily affected by the surrounding structural environment, so that the penetration and roundness of the channel holes in this region are greatly affected. [0003] Therefore, how to provide a semiconductor structure and its preparation method is necessary to solve the above-mentioned problems in the prior art. ...
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IPC IPC(8): H01L27/11524H01L27/11556H01L27/1157H01L27/11582H10B41/35H10B41/27H10B43/27H10B43/35
CPCH10B41/35H10B41/27H10B43/35H10B43/27
Inventor 刘高山黄海辉张福涛张天翼陈晋刘隆冬张文杰
Owner YANGTZE MEMORY TECH CO LTD