Row scanning circuit in CMOS image sensor

Abstract

The invention discloses a line scanning circuit in a CMOS image sensor. The line scanning circuit comprises a first module composed of a shift register chain and a local clock control module, a secondmodule composed of a non-overlapping processing circuit array, and a third module composed of a data line driving circuit. A shift register triggers clock partitioning local processing, so that the power consumption is reduced, and the possibility of wrong data output caused by mis-overturning is reduced; a multiplexing non-overlapping processing circuit is adopted, so that the chip area and thepower consumption overhead are reduced; a long data bus is segmented, and a latch buffer unit is inserted into the tail end of each segment, so that high-speed correct data reading under a small buffer size is realized.

Description

technical field [0001] The invention relates to the field of image sensors, in particular to a row scanning circuit in a CMOS image sensor. Background technique [0002] CMOS image sensors are widely used in many fields such as consumer electronics, high-definition surveillance, machine vision, space imaging, and medical imaging due to their advantages of low cost, low power consumption, and high integration. With the continuous increase of the pixel array scale and the gradual increase of the frame rate, the requirement for the data readout rate is also higher and higher. like figure 1 As shown, in a general CMOS image sensor, after the pixel array is exposed, the photoelectrons accumulated in the pixel are converted into a voltage signal inside the pixel, and the signal is amplified by the internal circuit of the pixel and the CSL (Current Source Load) circuit composed of the column-level current source load. The output of the circuit is amplified by the column-level var...

AI Technical Summary

Problems solved by technology

[0012] The purpose of the present invention is to provide a line scan circuit in a CMOS image sensor, to solve the waste of power consumption and data errors in the line scan circuit in the prior art, and to use a controllable delay unit to process the gate signal. The overlapping circuit scale is large. , and high data bus driver requirements, difficult chip layout and other issues

Images