Operational circuit of neural network

Abstract

The invention discloses an operational circuit of a neural network, and belongs to hardware implementation of the neural network. According to the method, scaling factors are configured for output data of a multiplier in convolution calculation so as to dynamically adjust the size of the output data; the calculated result data is dynamically quantitized during accumulation operation in convolutionto ensure the effective precision of the data so as to keep the scale of the data on the same layer uniform, and saturated interception is adaptively performed through data overflow detection duringinterception operation of the result data. According to the invention, threshold judgment is carried out on the data entering the multiplier based on the proposed self-adaptive threshold adjustment technology; therefore, under the condition that the precision is guaranteed, part of the numbers close to the zero value bypass multiplication calculation, and based on the proposed configurable compression transmission technology, configurable improvement is conducted on the run length coding mode, so that the run length coding mode meets different network compression requirements. According to theinvention, the data precision of the neural network reasoning process is improved, and the hardware resource overhead is saved.

Description

technical field [0001] The invention belongs to the technical field of artificial intelligence, and specifically relates to a hardware implementation of a neural network. Background technique [0002] Neural network hardware refers to a hardware system that supports the scale of the simulated neural network model and the speed of neural computing. Its main implementation hardware includes FPGA (Field Programmable Gate Array) implementation, neural chip and DSP (Digital Signal Processing) accelerator board, etc. Its hardware The core of the realization is the design of the neural network architecture. As an important part of the implementation of artificial intelligence technology, neural network hardware has gradually become a research hotspot. Especially for the architecture design of neural network hardware, it has been widely used in cloud, terminal and other applications. application. [0003] The main function of the neural network hardware is to accelerate the neural ...

AI Technical Summary

Problems solved by technology

[0004] At present, most of the neural network hardware design focuses on the inference speed of the neural network, and the accuracy requirements are low; or the accuracy requirements are reduced in order to save hardware resources; or the accuracy requirements are high, but there is no dynamic adjustment. The flexibility, so that it can only serve a specific task requirement in a single way, lacking generalization ability

Although the weight pruning and hardware zero-jumping operations can make the neural network sparse and reduce the number of multiplication operations to a certain extent, the pruning operation of the neural network weight usually brings a certain degree of precision loss. The greater the weight of the value, the greater the loss of precision. Therefore, it is necessary for the designer to adjust the sparsity of the pruned neural network subjectively for different neural networks and applications, and adaptive adjustment cannot be achieved.

Although the compression and transmission of weights through run-length coding can increase transmission speed and reduce transmission power consumption, this coding compression method lacks flexibility and cannot meet different neural network compression requirements, such as determining the length of the compressed data according to the length and width of the feature map. and many more

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