Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The forming method comprises the following steps: providing a substrate, forming a well region and a drift region in thesubstrate, forming a gate structure on the substrate, forming an active region in the well region on one side of the gate structure, forming a drain region in the drift region on the other side of the gate structure, and forming an interlayer dielectric layer on the substrate exposed out of the gate structure; etching a part of the interlayer dielectric layer above the source region and the drainregion to form an initial contact hole; etching the bottom of the initial contact hole and the interlayer dielectric layer on one side, close to the drain region, of the gate structure to form a contact hole exposing the source region and the drain region, and a deep groove located on one side of the gate structure, wherein the bottom of the deep groove is located in the interlayer dielectric layer and is lower than the top of the gate structure; and forming a contact hole plug located in the contact hole and a shielding plug located in the deep groove. According to the invention, the initialcontact hole is firstly formed, so that the bottom of the deep groove is still provided with a part of the interlayer dielectric layer, and the probability of bridging between the shielding plug andthe gate structure or the substrate is reduced.

Description

technical field [0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background technique [0002] With the rapid development of the semiconductor industry, PIC (power integrated circuit, power integrated circuit) has been continuously used in many fields. Lateral diffusion metal oxide semiconductor transistor (LDMOS) plays an important role in the design and manufacture of integrated circuits. Important position. LDMOS transistors generally need to have higher breakdown voltage (BV) and lower turn-on resistance (Ron) in use to improve transistor performance. [0003] In LDMOS transistors, since the drain terminal has to withstand a large voltage, the local electric field is very strong, so it is easy to generate hot carriers (hot electrons or hot holes), thereby causing hot carrier damage (hot carrier damage). question. The injection of hot electr...

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Problems solved by technology

It is difficult for hot holes to carry out effective charge balance and neutralization, so it is easy to generate an electric field in the vertical direction, which in turn affects the BV and Ron of the LDMOS transistor.

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