3D memory device

Abstract

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a storage stack including alternating conductive layers and dielectric layers above the peripheral circuit, an N-type doped semiconductor layer above the storage stack, A plurality of channel structures each extending vertically through the memory stack into the N-type doped semiconductor layer, and a source contact portion above the memory stack and in contact with the N-type doped semiconductor layer. The upper end of each of the plurality of channel structures is flush with or below the top surface of the N-type doped semiconductor layer.

Description

technical field [0001] Embodiments of the present disclosure relate to three-dimensional (3D) memory devices and fabrication methods thereof. Background technique [0002] Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and fabrication techniques. However, as the feature size of memory cells approaches the lower limit, planar processes and fabrication techniques become challenging and costly. Therefore, the storage density of planar memory cells approaches the upper limit. [0003] 3D memory architectures can address density limitations in planar memory cells. A 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. Contents of the invention [0004] Embodiments of 3D memory devices and methods for forming the same are disclosed herein. [0005] In one example, a 3D memory device includes a substrate, a peripheral circuit on the ...

AI Technical Summary

Problems solved by technology

However, as the feature size of memory cells approaches the lower limit, planar processes and fabrication techniques become challenging and costly

Therefore, the storage density of planar memory cells approaches the upper limit

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