Self-adaptive BIST test method for improving fault coverage rate

Abstract

The invention discloses a self-adaptive BIST test method for improving a fault coverage rate. The self-adaptive BIST test method is realized through an SRAM test control module, a fault pre-analysis module and an algorithm generation module. The SRAM test control module controls the working voltage, temperature, process and the like of the to-be-tested SRAM storage array, so that the SRAM exposesmore fault behaviors in different working environments, and the escape rate of faults is reduced; the fault pre-analysis module is used for pre-judging possible faults in the storage array in advance,a judgment result is input into the algorithm generation module, the algorithm generation module reconstructs an optimal algorithm of the storage array in the current environment and generates a newBIST circuit, and efficient and rapid fault testing is carried out on the storage array. The technology breaks through the limitation of a traditional algorithm, and can improve the fault coverage rate and reduce the test cost.

Description

technical field [0001] The invention belongs to the field of SRAM testing and specifically proposes an adaptive BIST testing method for improving fault coverage. Background technique [0002] In the process of rapid development of integrated circuits, high integration, high stability and strong battery life have become important indicators for measuring products. However, with the continuous reduction of chip size, the continuous reduction of voltage, and even the Small manufacturing defects pose a huge challenge to the stability of SRAM. Various unfavorable factors cause the threshold voltage mismatch of adjacent transistors in the storage array. The robustness of SRAM is getting worse and worse, and the ability to read and write is getting worse. Even As a result, reading and writing failed, and the error rate soared. In the existing research results, no algorithm can completely cover all kinds of failures caused by various unfavorable factors. And any soft fault that es...

AI Technical Summary

Problems solved by technology

[0002] In the process of rapid development of integrated circuits, high integration, high stability and strong battery life have become important indicators for measuring products. However, with the continuous reduction of chip size, the continuous reduction of voltage, and even the Small manufacturing defects pose a huge challenge to the stability of SRAM. Various unfavorable factors cause the threshold voltage mismatch of adjacent transistors in the storage array. The robustness of SRAM is getting worse and worse, and the ability to read and write is getting worse. Even Causes read and write failures, and the error rate soars

In the existing research results, no algorithm can completely cover all kinds of failures caused by various unfavorable factors

Any escaping soft faults may significantly affect the reliability of the product

There are also many researchers who have calculated specific algorithms for some complex dynamic stability faults, but usually these algorithms will face the problems of high complexity, long test time and expensive test costs, so how to solve the limitations of the algorithm and optimize the algorithm Short test time and power consumption, reducing test cost has become the breakthrough point of current research technology

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