High-speed data communication system and method

Abstract

The present invention provides a high-speed data communication system and method, comprising: VPX bus backplane: including a plurality of standard slots, the slots are inserted into boards of corresponding modules to realize high-speed signal interconnection between modules on the backplane; exchange Module: Provide high-speed data channels, high-speed data auxiliary channels and high-speed control channels for the slots of each functional board to realize high-speed data communication between each slot; power module: used to provide power for each slot; CPU computing module: for The high-speed data transmitted between the slots provides computing services. The data transmission and reception of the present invention adopts the asynchronous transmission and reception design of the double-loop four-linked list, which can perform high-speed data transmission and reception well, and the consumption of CPU and memory is relatively stable, and will not cause the situation of occupying a large amount of memory; Chain configuration water level technology, FPGA RapidIO flow control, to ensure the balance of the capabilities of the sending end and the receiving end.

Description

Technical field [0001] The present invention relates to the field of data communication, and in particular, to a high speed data communication system and method. In particular, there is a high-speed data communication method based on radar information processing computer RAPIDIO bus. Background technique [0002] Rapidio is an open interconnect technology standard for chip, inter-board interconnect systems. It has the characteristics of high transmission efficiency, flexible topology, and high reliability, have been widely used in various systems. [0003] In some RAPIDIO-based transmission systems, there is highly high-sensitive performance and transmission rates. Considering the time sensitivity, the data is not uniformly transmitted, and the data rate has a large randomness, so short data frame can only be used. When the instantaneous transmission rate is high, a large number of doorbells or mailbox (Mailbox) data transmission, the receiving end CPU will respond frequently, wh...

AI Technical Summary

Problems solved by technology

This will greatly increase the CPU system overhead, reduce the transmission rate rapidly, and even cause the CPU to fail to work normally.

[0004] RapidIO is an embedded high-speed data bus. CPU-side programmers generally need to combine RapidIO routing and enumeration configuration, RapidIO address mapping, operating system physical and virtual memory mapping, DMA data reading and writing, and doorbell data sending and receiving. RapidIO bus development technology such as sending and receiving of message data, due to professional limitations, the cost of learning and development is too high for radar programmers;

[0005] There is an imbalance in RapidIO data communication between CPU and FPGA. One imbalance is that FPAG’s processing of RapidIO protocol is generally higher than that of most CPUs (even with the assistance of bridge chips such as ts i721), and the other imbalance is It is the CPU that needs to actively read the RapidIO data from the FPGA in real time, otherwise there will be data overflow. In this case, if the data synchronization is not handled properly, it is very easy for the device to crash or crash;

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