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Asynchronous data interaction method and system based on ARM + FPGA + DSP architecture

A technology of asynchronous data and interactive methods, applied in the field of control systems, can solve problems such as low reliability of asynchronous data transmission and uncertain delay, and achieve the effects of improving communication efficiency, ensuring correctness, and stable and reliable transmission

Active Publication Date: 2020-12-29
CSR ZHUZHOU ELECTRIC LOCOMOTIVE RES INST
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] The present invention provides an asynchronous data interaction method and system based on ARM+FPGA+DSP architecture, which is used to solve the problem of low reliability of asynchronous data transmission and uncertain delay in the existing ARM+FPGA+DSP control system application architecture technical problem

Method used

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  • Asynchronous data interaction method and system based on ARM + FPGA + DSP architecture
  • Asynchronous data interaction method and system based on ARM + FPGA + DSP architecture
  • Asynchronous data interaction method and system based on ARM + FPGA + DSP architecture

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Embodiment 1

[0074] This embodiment illustrates the structure of the data frame and its application on the basis of the above-mentioned principle of the present invention.

[0075] In order to ensure the reliability and stability of data transmission, in the communication protocol, this embodiment adds a heartbeat signal to judge whether there is new data input. At the same time, a CRC checksum is added to the protocol to ensure that the data is Integrity in. This embodiment adopts the following communication protocol for communication:

[0076] The structure of the data frame that the ARM of the present embodiment sends to DSP is as Figure 6 As shown, the data frame includes a 5-byte data header, a 1-byte data checksum, and variable-length data content. The data header includes a 2-byte heartbeat signal and a 1-byte function code. 2 bytes of data length information. In order to improve the efficiency of data interaction, it is stipulated that the data length of a frame is up to 64 byt...

Embodiment 2

[0088] This embodiment describes the reverse data transmission from DSP to ARM. This embodiment can be used in combination with Embodiment 1.

[0089] When the DSP needs to send data to the ARM, the specific transmission process is as follows Figure 8 shown.

[0090] 1) The DSP encapsulates the data to be sent according to the format of the data transmission protocol, and sends the encapsulated data to the FPGA through the UPP interface;

[0091] 2) The FPGA writes the received UPP data into the internal dual-port RAM;

[0092] 3) ARM checks whether there is any data received by means of circular query. That is, ARM checks the data in the dual-port RAM every fixed period. If the heartbeat signal of the data in the dual-port RAM is the current ARM heartbeat signal data plus 1, it means that there is data reception.

Embodiment 3

[0094] This embodiment is basically the same as Embodiment 1, the difference is that the FPGA and the DSP in this embodiment adopt dual-port RAM communication, such as Figure 9 Shown: When the FPGA receives the ARM data and sends it to the DSP through the dual-port RAM, the DSP checks whether there is new data to receive by polling. The real-time performance of this embodiment is worse than that of Embodiment 1, and the hardware resource consumption of the increased FPGA is more than that of Embodiment 1.

[0095] To sum up, the present invention can significantly improve communication efficiency; through the asynchronous data interaction method, stable and reliable data transmission among the three can be realized. And add heartbeat information and data verification to the data frame, analyze the data according to the change of the heartbeat information, improve the efficiency of data analysis, avoid unnecessary data analysis; data verification can ensure the correctness of ...

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Abstract

The invention discloses an asynchronous data interaction method and system based on an ARM + FPGA + DSP architecture. The method comprises the steps that when an ARM needs to transmit data to a DSP, the ARM packages to-be-transmitted data, writes a packaged data frame into a double-port RAM in an FPGA, and then transmits a write completion signal to the FPGA after packaging is completed; after receiving the write completion signal, the FPGA sends the data frame in the dual-port RAM in the FPGA to the DSP; and the DSP receives the data frame. According to the method and system, the reliabilityand transmission efficiency of data transmission can be improved, the bit error rate of data transmission is reduced, and the user experience is improved.

Description

technical field [0001] The invention relates to the field of control systems, in particular to an asynchronous data interaction method and system based on an ARM+FPGA+DSP architecture. Background technique [0002] At present, the commonly used control system application architecture is ARM+FPGA+DSP. In this system architecture, ARM mainly provides rich peripheral interfaces and storage resources, and can realize real-time communication with the host computer through the Ethernet port; FPGA mainly completes Data preprocessing and conversion; DSP is mainly responsible for digital signal processing and calculation. This system architecture enhances the flexibility of system control and calculation, which is conducive to improving the safety and reliability of the entire system. However, to measure the overall performance of a system, it is necessary to consider the communication interface and communication protocol between the three devices to avoid the consumption of data com...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G05B19/042
CPCG05B19/0421G05B2219/2214G05B2219/25179
Inventor 李益李程王成杰文宇良付建国谭磊
Owner CSR ZHUZHOU ELECTRIC LOCOMOTIVE RES INST
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