Method for manufacturing semiconductor power device
A technology of power devices and manufacturing methods, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems affecting the withstand voltage of semiconductor power devices, and achieve the effect of unaffected withstand voltage and reduced thickness
Active Publication Date: 2021-01-26
SUZHOU ORIENTAL SEMICONDUCTOR CO LTD
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Problems solved by technology
In the manufacturing method of semiconductor power devices in the prior art, in order to ensure the quality of the polysilicon gate, it is necessary to form a first dielectric layer with sufficient thickness, but the thickness of the first dielectric layer will affect the charge depletion at the bottom of the trench, thereby affecting the semiconductor power. device withstand voltage
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[0030] The technical solutions of the present invention will be fully described below in conjunction with the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some, not all, embodiments of the present invention. At the same time, in order to clearly illustrate the specific implementation of the present invention, the schematic diagrams listed in the accompanying drawings of the specification magnify the thickness of the layers and regions described in the present invention, and the listed figures do not represent the actual size.
[0031] Figure 1 to Figure 6 It is a schematic cross-sectional structure diagram of the main structure in the manufacturing process of an embodiment of the manufacturing method of the semiconductor power device provided by the present invention.
[0032] First, if figure 1 As shown, a first insulating layer 31 is formed on the provided n-type substrate 20. The n-type substrate 20 is usual...
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The invention belongs to the technical field of semiconductor power devices, and particularly discloses a method for manufacturing a semiconductor power device, which comprises the following steps of:etching an n-type substrate in a self-aligned manner by taking a first insulating layer, a second insulating layer and a third insulating layer as masks, forming a second groove in the n-type substrate, and forming a fourth insulating layer and a grid in the second groove. According to the method for manufacturing the semiconductor power device, the forming quality of the grid electrode is not limited by the thickness of the second insulating layer, and the thickness of the second insulating layer can be reduced under the condition of ensuring the quality of the grid electrode, so that the withstand voltage of the semiconductor power device is not influenced.
Description
technical field [0001] The invention belongs to the technical field of semiconductor power devices, in particular to a manufacturing method of semiconductor power devices. Background technique [0002] A manufacturing method of a semiconductor power device in the prior art includes: forming a hard mask layer on a provided silicon substrate, using a photolithography process to define a trench position, and then etching away the hard mask layer at the trench position ; use the etched hard mask layer as a mask to etch the silicon substrate to form a trench; cover the bottom surface and sides of the trench to form a first dielectric layer; deposit the first polysilicon layer, the first polysilicon layer The crystalline silicon layer completely fills the trench formed with the first dielectric layer and extends to the outside of the trench; performing polysilicon etching back removes the first polysilicon layer outside the trench, and the remaining first polysilicon layer after e...
Claims
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Patent Timeline
Login to View More IPC IPC(8): H01L21/28H01L21/308
CPCH01L21/28035H01L21/28114H01L21/3086H01L21/3083H01L29/66734H01L29/66719H01L29/407H01L29/401H01L29/7813
Inventor 刘伟徐真逸毛振东王鑫
Owner SUZHOU ORIENTAL SEMICONDUCTOR CO LTD