DDR3 function testing platform based on digital signal integrated circuit testing system EVA100

Abstract

The invention belongs to the field of digital integrated circuit testing, and particularly relates to a DDR3 function testing platform based on a digital signal integrated circuit testing system EVA100. The DDR3 function testing platform comprises an EVA100 testing machine, an FPGA central control board and a DDR3 chip to be tested, wherein the FPGA central control board comprises an FPGA minimumsystem, a power distribution network, an LED circuit, a DDR3 circuit and an EVA control interface circuit. The FPGA minimum system comprises an FPGA chip, a clock circuit, a reset circuit and a configuration circuit. The FPGA chip comprises a signal synchronous processing module and a DDR3 measurement and control module, the signal synchronous processing module realizes data transceiving with an EVA100 testing machine through an EVA control interface circuit, performs synchronous analysis on data frames from the EVA100 testing machine, selects a testing operation mode according to an analysisresult, and the DDR3 measurement and control module is used for completing specified function testing operation, and finally synchronously feeding back a testing result to the EVA100 testing machine;and the DDR3 measurement and control module realizes testing flow control and function test of the DDR3 chip to be tested.

Description

technical field [0001] The invention belongs to the field of digital integrated circuit testing, in particular to a DDR3 function testing platform based on a digital signal integrated circuit testing system EVA100. Background technique [0002] DDR3 is the third generation of high-performance DDR SDRAM proposed to adapt to the development of computer technology. At present, the data rate span of DDR3 starts from 800Mbps to 1.6Gbps. While bringing users faster performance experience, DDR3 can maintain a low Power consumption, about 20% less than previous generation DDR2. With the rapid development of the electronic information technology industry, the requirements for the operating speed of hardware devices are getting higher and higher, and it is more and more common to use DDR3 as a cache in the design, so efficient and low-cost DDR3 test solutions will be the focus of attention. [0003] Due to the increase in speed, the test platform must provide a higher test frequency ...

AI Technical Summary

Problems solved by technology

[0005] 1. DDR3 has a high operating frequency and must rely on larger-scale integrated test systems, such as V93000 HSM3G, T5503, etc., which are more cost-effective. However, the test machine must still use dedicated resource modules to complete the test for DDR3

At the same time, DDR3 has higher requirements for electromagnetic compatibility, making test board production more difficult, and the entire test development cost is higher

[0006] 2. DDR3 has a large capacity, and the test time at a lower frequency increases exponentially with the increase in capacity

[0007] 3. Neither the large-scale integrated test system J750 nor the digital signal integrated circuit test system EVA100 has direct test conditions for DDR3, and there is no effective DDR3 test solution based on the EVA100 test system at present

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