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Electrostatic discharge protection structure and manufacturing method thereof

A technology of electrostatic discharge protection and manufacturing method, applied in circuits, electrical components, electrical solid devices, etc., can solve problems such as failure of ESD devices, and achieve the effects of reducing substrate resistance difference, improving reliability, and alleviating conduction.

Pending Publication Date: 2021-02-12
YANGTZE MEMORY TECH CO LTD
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  • Abstract
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  • Claims
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Problems solved by technology

[0006] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide an electrostatic discharge protection structure and a manufacturing method thereof, which are used to solve the problem that the electrostatic discharge protection structure in the prior art is likely to cause ESD device failure, so as to improve the electrostatic discharge protection structure. Reliability of Protective Structure

Method used

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  • Electrostatic discharge protection structure and manufacturing method thereof
  • Electrostatic discharge protection structure and manufacturing method thereof
  • Electrostatic discharge protection structure and manufacturing method thereof

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Embodiment Construction

[0050] Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

[0051] For example, when describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, which should not limit the protection scope of the present invention. In addition, the three-dimensional space dimensions of length, width and depth sho...

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Abstract

The invention provides an electrostatic discharge protection structure and a manufacturing method thereof. The structure comprises a central region and an edge region surrounding the central region, wherein the central region comprises a trap with higher doping concentration, so that the substrate resistance of an MOS transistor in the central region can be reduced, the substrate resistance difference between the MOS transistor in the central region and the MOS transistor in the edge region is reduced, the conduction voltage of the MOS transistor in the central region is improved, the premature conduction of the MOS transistor in the central region is effectively relieved, the failure probability of the electrostatic discharge protection structure is reduced, and the reliability of the electrostatic discharge protection structure is improved.

Description

technical field [0001] The invention belongs to the field of semiconductor integrated circuits, and relates to an electrostatic discharge protection structure and a manufacturing method thereof. Background technique [0002] Electro-Static discharge (ESD for short) is a rapid neutralization process of charges. Due to the high ESD voltage, ESD will bring destructive consequences to the integrated circuit, resulting in the failure of the integrated circuit. At present, all kinds of integrated circuits are widely used in various electrical appliances and fields, and the damage of integrated circuits caused by ESD every year causes very serious economic losses. In order to reduce the losses caused by ESD, the ESD protection of integrated circuits Capability is a problem that must be considered in chip design at present. [0003] The input and output pads (IO PAD) of high-voltage devices are usually protected by high-voltage NMOS, using a grounded-gate NMOS (Grounded-Gate NMOS,...

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Application Information

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IPC IPC(8): H01L27/02H01L21/82
CPCH01L27/0266H01L27/0296H01L21/82
Inventor 王欣李志国孙超江宁
Owner YANGTZE MEMORY TECH CO LTD
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